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<a name="details" id="details"></a><h2 class="groupheader">Overview</h2>
<div class="textblock"><p>This header file contains identifiers and basic driver functions for the <a class="el" href="struct_x_dma_pcie.html" title="The XDmaPcie driver instance data. ">XDmaPcie</a> device driver. </p>
<dl class="section note"><dt>Note</dt><dd>None.</dd></dl>
<pre>
MODIFICATION HISTORY:</pre><pre>Ver   Who  Date     Changes
</p>
<hr/>
<p>
1.0     tk      01/30/2019      First release
</pre> </div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:a736c70d6aa883f4d252670658e3b95ad"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a736c70d6aa883f4d252670658e3b95ad">XDmaPcie_ReadReg</a>(BaseAddress, RegOffset)&#160;&#160;&#160;Xil_In32((BaseAddress) + (RegOffset))</td></tr>
<tr class="memdesc:a736c70d6aa883f4d252670658e3b95ad"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to read register.  <a href="#a736c70d6aa883f4d252670658e3b95ad">More...</a><br/></td></tr>
<tr class="separator:a736c70d6aa883f4d252670658e3b95ad"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afa180a178e9501f6238f5a5fbbd62a69"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#afa180a178e9501f6238f5a5fbbd62a69">XDmaPcie_WriteReg</a>(BaseAddress, RegOffset, Data)&#160;&#160;&#160;Xil_Out32((BaseAddress) + (RegOffset), (Data))</td></tr>
<tr class="memdesc:afa180a178e9501f6238f5a5fbbd62a69"><td class="mdescLeft">&#160;</td><td class="mdescRight">Macro to write register.  <a href="#afa180a178e9501f6238f5a5fbbd62a69">More...</a><br/></td></tr>
<tr class="separator:afa180a178e9501f6238f5a5fbbd62a69"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Register offsets for this device.</p>
<p>Some of the registers are configurable at hardware build time such that may or may not exist in the hardware. </p>
</div></td></tr>
<tr class="memitem:a1083266540141374178a8efd47a8c838"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a1083266540141374178a8efd47a8c838">XDMAPCIE_PCIE_CORE_OFFSET</a>&#160;&#160;&#160;0x000</td></tr>
<tr class="memdesc:a1083266540141374178a8efd47a8c838"><td class="mdescLeft">&#160;</td><td class="mdescRight">PCI Express hard core configuration register offset.  <a href="#a1083266540141374178a8efd47a8c838">More...</a><br/></td></tr>
<tr class="separator:a1083266540141374178a8efd47a8c838"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a16f5d7b6b585ac5ac0fcd5189889c104"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a16f5d7b6b585ac5ac0fcd5189889c104">XDMAPCIE_VSECC_OFFSET</a>&#160;&#160;&#160;0x128</td></tr>
<tr class="memdesc:a16f5d7b6b585ac5ac0fcd5189889c104"><td class="mdescLeft">&#160;</td><td class="mdescRight">VSEC Capability Register.  <a href="#a16f5d7b6b585ac5ac0fcd5189889c104">More...</a><br/></td></tr>
<tr class="separator:a16f5d7b6b585ac5ac0fcd5189889c104"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae6596b5eb3e9c22bc43c90a57ed9945f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#ae6596b5eb3e9c22bc43c90a57ed9945f">XDMAPCIE_VSECH_OFFSET</a>&#160;&#160;&#160;0x12C</td></tr>
<tr class="memdesc:ae6596b5eb3e9c22bc43c90a57ed9945f"><td class="mdescLeft">&#160;</td><td class="mdescRight">VSEC Header Register.  <a href="#ae6596b5eb3e9c22bc43c90a57ed9945f">More...</a><br/></td></tr>
<tr class="separator:ae6596b5eb3e9c22bc43c90a57ed9945f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3608f25f453e0135ff2e2bd6a160533c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a3608f25f453e0135ff2e2bd6a160533c">XDMAPCIE_BI_OFFSET</a>&#160;&#160;&#160;0x130</td></tr>
<tr class="memdesc:a3608f25f453e0135ff2e2bd6a160533c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bridge Info Register.  <a href="#a3608f25f453e0135ff2e2bd6a160533c">More...</a><br/></td></tr>
<tr class="separator:a3608f25f453e0135ff2e2bd6a160533c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac669dec8e84593dc82387d7abb9e27ae"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#ac669dec8e84593dc82387d7abb9e27ae">XDMAPCIE_BSC_OFFSET</a>&#160;&#160;&#160;0x134</td></tr>
<tr class="memdesc:ac669dec8e84593dc82387d7abb9e27ae"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bridge Status and Control Register.  <a href="#ac669dec8e84593dc82387d7abb9e27ae">More...</a><br/></td></tr>
<tr class="separator:ac669dec8e84593dc82387d7abb9e27ae"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1a466d7f94958ad960844918169a95ef"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a1a466d7f94958ad960844918169a95ef">XDMAPCIE_ID_OFFSET</a>&#160;&#160;&#160;0x138</td></tr>
<tr class="memdesc:a1a466d7f94958ad960844918169a95ef"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Decode Register.  <a href="#a1a466d7f94958ad960844918169a95ef">More...</a><br/></td></tr>
<tr class="separator:a1a466d7f94958ad960844918169a95ef"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a241506bc1816800ebc206d77b9d26436"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a241506bc1816800ebc206d77b9d26436">XDMAPCIE_IM_OFFSET</a>&#160;&#160;&#160;0x13C</td></tr>
<tr class="memdesc:a241506bc1816800ebc206d77b9d26436"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Mask Register.  <a href="#a241506bc1816800ebc206d77b9d26436">More...</a><br/></td></tr>
<tr class="separator:a241506bc1816800ebc206d77b9d26436"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a31d2fdd979d3087f69bd97eb52b4c499"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a31d2fdd979d3087f69bd97eb52b4c499">XDMAPCIE_BL_OFFSET</a>&#160;&#160;&#160;0x140</td></tr>
<tr class="memdesc:a31d2fdd979d3087f69bd97eb52b4c499"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bus Location Register.  <a href="#a31d2fdd979d3087f69bd97eb52b4c499">More...</a><br/></td></tr>
<tr class="separator:a31d2fdd979d3087f69bd97eb52b4c499"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a571a1cd55e8f810fb91fcfebc441ee46"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a571a1cd55e8f810fb91fcfebc441ee46">XDMAPCIE_PHYSC_OFFSET</a>&#160;&#160;&#160;0x144</td></tr>
<tr class="memdesc:a571a1cd55e8f810fb91fcfebc441ee46"><td class="mdescLeft">&#160;</td><td class="mdescRight">Physical status and Control Register.  <a href="#a571a1cd55e8f810fb91fcfebc441ee46">More...</a><br/></td></tr>
<tr class="separator:a571a1cd55e8f810fb91fcfebc441ee46"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab68d32651b96f4c8a6cc6c7549509c82"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#ab68d32651b96f4c8a6cc6c7549509c82">XDMAPCIE_RPSC_OFFSET</a>&#160;&#160;&#160;0x148</td></tr>
<tr class="memdesc:ab68d32651b96f4c8a6cc6c7549509c82"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Status &amp; Control Register.  <a href="#ab68d32651b96f4c8a6cc6c7549509c82">More...</a><br/></td></tr>
<tr class="separator:ab68d32651b96f4c8a6cc6c7549509c82"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2c7a2d9d74f6b92651fe50bddbb5e594"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a2c7a2d9d74f6b92651fe50bddbb5e594">XDMAPCIE_RPMSIB_UPPER_OFFSET</a>&#160;&#160;&#160;0x14C</td></tr>
<tr class="memdesc:a2c7a2d9d74f6b92651fe50bddbb5e594"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port MSI Base 1 Register Upper 32 bits from 64 bit address are written.  <a href="#a2c7a2d9d74f6b92651fe50bddbb5e594">More...</a><br/></td></tr>
<tr class="separator:a2c7a2d9d74f6b92651fe50bddbb5e594"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a39e3da3783cd1ae36538dda9353bd662"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a39e3da3783cd1ae36538dda9353bd662">XDMAPCIE_RPMSIB_LOWER_OFFSET</a>&#160;&#160;&#160;0x150</td></tr>
<tr class="memdesc:a39e3da3783cd1ae36538dda9353bd662"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port MSI Base 2 Register Lower 32 bits from 64 bit address are written.  <a href="#a39e3da3783cd1ae36538dda9353bd662">More...</a><br/></td></tr>
<tr class="separator:a39e3da3783cd1ae36538dda9353bd662"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a46d0aae62d5b3314d9eb4ef5830b4ec0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a46d0aae62d5b3314d9eb4ef5830b4ec0">XDMAPCIE_RPEFR_OFFSET</a>&#160;&#160;&#160;0x154</td></tr>
<tr class="memdesc:a46d0aae62d5b3314d9eb4ef5830b4ec0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Error FIFO Read Register.  <a href="#a46d0aae62d5b3314d9eb4ef5830b4ec0">More...</a><br/></td></tr>
<tr class="separator:a46d0aae62d5b3314d9eb4ef5830b4ec0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2d3fa8b6821762a92a973e4b1d341f12"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a2d3fa8b6821762a92a973e4b1d341f12">XDMAPCIE_RPIFR1_OFFSET</a>&#160;&#160;&#160;0x158</td></tr>
<tr class="memdesc:a2d3fa8b6821762a92a973e4b1d341f12"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Interrupt FIFO Read1 Register.  <a href="#a2d3fa8b6821762a92a973e4b1d341f12">More...</a><br/></td></tr>
<tr class="separator:a2d3fa8b6821762a92a973e4b1d341f12"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad5f6e8d589fe6f5a01e312a8f092799c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#ad5f6e8d589fe6f5a01e312a8f092799c">XDMAPCIE_RPIFR2_OFFSET</a>&#160;&#160;&#160;0x15C</td></tr>
<tr class="memdesc:ad5f6e8d589fe6f5a01e312a8f092799c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Interrupt FIFO Read2 Register.  <a href="#ad5f6e8d589fe6f5a01e312a8f092799c">More...</a><br/></td></tr>
<tr class="separator:ad5f6e8d589fe6f5a01e312a8f092799c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5c9801387aa82ecd82ef7eeb15224636"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a5c9801387aa82ecd82ef7eeb15224636">XDMAPCIE_AXIBAR2PCIBAR_0U_OFFSET</a>&#160;&#160;&#160;0x208</td></tr>
<tr class="memdesc:a5c9801387aa82ecd82ef7eeb15224636"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXIBAR 2 PCIBAR translation 0 upper 32 bits.  <a href="#a5c9801387aa82ecd82ef7eeb15224636">More...</a><br/></td></tr>
<tr class="separator:a5c9801387aa82ecd82ef7eeb15224636"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a51aeaa8592563052dfac4d5c7c5ee606"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a51aeaa8592563052dfac4d5c7c5ee606">XDMAPCIE_AXIBAR2PCIBAR_0L_OFFSET</a>&#160;&#160;&#160;0x20C</td></tr>
<tr class="memdesc:a51aeaa8592563052dfac4d5c7c5ee606"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXIBAR to PCIBAR translation 0 lower 32 bits.  <a href="#a51aeaa8592563052dfac4d5c7c5ee606">More...</a><br/></td></tr>
<tr class="separator:a51aeaa8592563052dfac4d5c7c5ee606"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a82dc968ee93525aa88ccf20114e44527"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a82dc968ee93525aa88ccf20114e44527">XDMAPCIE_AXIBAR2PCIBAR_1U_OFFSET</a>&#160;&#160;&#160;0x210</td></tr>
<tr class="memdesc:a82dc968ee93525aa88ccf20114e44527"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXIBAR to PCIBAR translation 1 upper 32 bits.  <a href="#a82dc968ee93525aa88ccf20114e44527">More...</a><br/></td></tr>
<tr class="separator:a82dc968ee93525aa88ccf20114e44527"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aae54b8461f7378ac04fdeb5003a40f5e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#aae54b8461f7378ac04fdeb5003a40f5e">XDMAPCIE_AXIBAR2PCIBAR_1L_OFFSET</a>&#160;&#160;&#160;0x214</td></tr>
<tr class="memdesc:aae54b8461f7378ac04fdeb5003a40f5e"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXIBAR to PCIBAR translation 1 lower 32 bits.  <a href="#aae54b8461f7378ac04fdeb5003a40f5e">More...</a><br/></td></tr>
<tr class="separator:aae54b8461f7378ac04fdeb5003a40f5e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a77ac31855b0e6d83ea7999a29a8ce4c8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a77ac31855b0e6d83ea7999a29a8ce4c8">XDMAPCIE_AXIBAR2PCIBAR_2U_OFFSET</a>&#160;&#160;&#160;0x218</td></tr>
<tr class="memdesc:a77ac31855b0e6d83ea7999a29a8ce4c8"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXIBAR to PCIBAR translation 2 upper 32 bits.  <a href="#a77ac31855b0e6d83ea7999a29a8ce4c8">More...</a><br/></td></tr>
<tr class="separator:a77ac31855b0e6d83ea7999a29a8ce4c8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab53d13c64564b4668256c817f5e0068b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#ab53d13c64564b4668256c817f5e0068b">XDMAPCIE_AXIBAR2PCIBAR_2L_OFFSET</a>&#160;&#160;&#160;0x21C</td></tr>
<tr class="memdesc:ab53d13c64564b4668256c817f5e0068b"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXIBAR to PCIBAR translation 2 lower 32 bits.  <a href="#ab53d13c64564b4668256c817f5e0068b">More...</a><br/></td></tr>
<tr class="separator:ab53d13c64564b4668256c817f5e0068b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab73660262ed83e2db03302cc57a1b6aa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#ab73660262ed83e2db03302cc57a1b6aa">XDMAPCIE_AXIBAR2PCIBAR_3U_OFFSET</a>&#160;&#160;&#160;0x220</td></tr>
<tr class="memdesc:ab73660262ed83e2db03302cc57a1b6aa"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXIBAR to PCIBAR translation 3 upper 32 bits.  <a href="#ab73660262ed83e2db03302cc57a1b6aa">More...</a><br/></td></tr>
<tr class="separator:ab73660262ed83e2db03302cc57a1b6aa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6b5c1a0ce298b54d802396314a585981"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a6b5c1a0ce298b54d802396314a585981">XDMAPCIE_AXIBAR2PCIBAR_3L_OFFSET</a>&#160;&#160;&#160;0x224</td></tr>
<tr class="memdesc:a6b5c1a0ce298b54d802396314a585981"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXIBAR to PCIBAR translation 3 lower 32 bits.  <a href="#a6b5c1a0ce298b54d802396314a585981">More...</a><br/></td></tr>
<tr class="separator:a6b5c1a0ce298b54d802396314a585981"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a117eb6e0c55cf3eb474c087becaa3dfb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a117eb6e0c55cf3eb474c087becaa3dfb">XDMAPCIE_AXIBAR2PCIBAR_4U_OFFSET</a>&#160;&#160;&#160;0x228</td></tr>
<tr class="memdesc:a117eb6e0c55cf3eb474c087becaa3dfb"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXIBAR to PCIBAR translation 4 upper 32 bits.  <a href="#a117eb6e0c55cf3eb474c087becaa3dfb">More...</a><br/></td></tr>
<tr class="separator:a117eb6e0c55cf3eb474c087becaa3dfb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a59bbd07ab35b7dbe8534d41deba0490e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a59bbd07ab35b7dbe8534d41deba0490e">XDMAPCIE_AXIBAR2PCIBAR_4L_OFFSET</a>&#160;&#160;&#160;0x22C</td></tr>
<tr class="memdesc:a59bbd07ab35b7dbe8534d41deba0490e"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXIBAR to PCIBAR translation 4 lower 32 bits.  <a href="#a59bbd07ab35b7dbe8534d41deba0490e">More...</a><br/></td></tr>
<tr class="separator:a59bbd07ab35b7dbe8534d41deba0490e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afae77b2b76afd561a3d35442a58215e4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#afae77b2b76afd561a3d35442a58215e4">XDMAPCIE_AXIBAR2PCIBAR_5U_OFFSET</a>&#160;&#160;&#160;0x230</td></tr>
<tr class="memdesc:afae77b2b76afd561a3d35442a58215e4"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXIBAR to PCIBAR translation 5 upper 32 bits.  <a href="#afae77b2b76afd561a3d35442a58215e4">More...</a><br/></td></tr>
<tr class="separator:afae77b2b76afd561a3d35442a58215e4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab63696750f01c882427fe3d0118756c5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#ab63696750f01c882427fe3d0118756c5">XDMAPCIE_AXIBAR2PCIBAR_5L_OFFSET</a>&#160;&#160;&#160;0x234</td></tr>
<tr class="memdesc:ab63696750f01c882427fe3d0118756c5"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXIBAR to PCIBAR translation 5 lower 32 bits.  <a href="#ab63696750f01c882427fe3d0118756c5">More...</a><br/></td></tr>
<tr class="separator:ab63696750f01c882427fe3d0118756c5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">IATU Programming Registers Offset</div></td></tr>
<tr class="memitem:acbc85cd7d570931c9fc11b2b006f25ab"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#acbc85cd7d570931c9fc11b2b006f25ab">XDMAPCIE_IATU_REGION_CNTRL_OFFSET</a>&#160;&#160;&#160;0x004</td></tr>
<tr class="memdesc:acbc85cd7d570931c9fc11b2b006f25ab"><td class="mdescLeft">&#160;</td><td class="mdescRight">EN/DE IATU transalation.  <a href="#acbc85cd7d570931c9fc11b2b006f25ab">More...</a><br/></td></tr>
<tr class="separator:acbc85cd7d570931c9fc11b2b006f25ab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae73a480f3fc21d558ba967eb130456f4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#ae73a480f3fc21d558ba967eb130456f4">XDMAPCIE_IATU_LWR_BASE_ADDR_OFFSET</a>&#160;&#160;&#160;0x008</td></tr>
<tr class="memdesc:ae73a480f3fc21d558ba967eb130456f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">ATU Lower Base Address.  <a href="#ae73a480f3fc21d558ba967eb130456f4">More...</a><br/></td></tr>
<tr class="separator:ae73a480f3fc21d558ba967eb130456f4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a23f3dd742a5d5c16771362ae05fb5855"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a23f3dd742a5d5c16771362ae05fb5855">XDMAPCIE_IATU_UPPER_BASE_ADDR_OFFSET</a>&#160;&#160;&#160;0x00C</td></tr>
<tr class="memdesc:a23f3dd742a5d5c16771362ae05fb5855"><td class="mdescLeft">&#160;</td><td class="mdescRight">ATU Upper Base Address.  <a href="#a23f3dd742a5d5c16771362ae05fb5855">More...</a><br/></td></tr>
<tr class="separator:a23f3dd742a5d5c16771362ae05fb5855"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7844054c17cc8874eebaaedba9b24cf4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a7844054c17cc8874eebaaedba9b24cf4">XDMAPCIE_IATU_LIMIT_ADDR_OFFSET</a>&#160;&#160;&#160;0x010</td></tr>
<tr class="memdesc:a7844054c17cc8874eebaaedba9b24cf4"><td class="mdescLeft">&#160;</td><td class="mdescRight">ATU Lmit Address.  <a href="#a7844054c17cc8874eebaaedba9b24cf4">More...</a><br/></td></tr>
<tr class="separator:a7844054c17cc8874eebaaedba9b24cf4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2b8df76648fe067cec116769e55a10f8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a2b8df76648fe067cec116769e55a10f8">XDMAPCIE_IATU_PCIE_LWR_ADDR_OFFSET</a>&#160;&#160;&#160;0x014</td></tr>
<tr class="memdesc:a2b8df76648fe067cec116769e55a10f8"><td class="mdescLeft">&#160;</td><td class="mdescRight">PCIe Lower Address.  <a href="#a2b8df76648fe067cec116769e55a10f8">More...</a><br/></td></tr>
<tr class="separator:a2b8df76648fe067cec116769e55a10f8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a032ceff8d0b842bad143b0c64227d1f4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a032ceff8d0b842bad143b0c64227d1f4">XDMAPCIE_IATU_PCIE_UPPER_ADDR_OFFSET</a>&#160;&#160;&#160;0x018</td></tr>
<tr class="memdesc:a032ceff8d0b842bad143b0c64227d1f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">PCIe Upper Address.  <a href="#a032ceff8d0b842bad143b0c64227d1f4">More...</a><br/></td></tr>
<tr class="separator:a032ceff8d0b842bad143b0c64227d1f4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afd733b204e82bc26f763f8b3b85297fa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#afd733b204e82bc26f763f8b3b85297fa">XDMAPCIE_IATU_MAX_ATU_SIZE_OFFSET</a>&#160;&#160;&#160;0x020</td></tr>
<tr class="memdesc:afd733b204e82bc26f763f8b3b85297fa"><td class="mdescLeft">&#160;</td><td class="mdescRight">ATU Max Size.  <a href="#afd733b204e82bc26f763f8b3b85297fa">More...</a><br/></td></tr>
<tr class="separator:afd733b204e82bc26f763f8b3b85297fa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">IATU Programming Register masks</div></td></tr>
<tr class="memitem:ac16ba889496220efc741c8253807c515"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#ac16ba889496220efc741c8253807c515">XDMAPCIE_CFG_TLP_TYPE0</a>&#160;&#160;&#160;0x4</td></tr>
<tr class="memdesc:ac16ba889496220efc741c8253807c515"><td class="mdescLeft">&#160;</td><td class="mdescRight">TYPE 0 to Config TLP.  <a href="#ac16ba889496220efc741c8253807c515">More...</a><br/></td></tr>
<tr class="separator:ac16ba889496220efc741c8253807c515"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a401d3214b790655f8f2afd71c9ec99f7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a401d3214b790655f8f2afd71c9ec99f7">XDMAPCIE_CFG_TLP_TYPE1</a>&#160;&#160;&#160;0x5</td></tr>
<tr class="memdesc:a401d3214b790655f8f2afd71c9ec99f7"><td class="mdescLeft">&#160;</td><td class="mdescRight">TYPE 1 to Config TLP.  <a href="#a401d3214b790655f8f2afd71c9ec99f7">More...</a><br/></td></tr>
<tr class="separator:a401d3214b790655f8f2afd71c9ec99f7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae8f262322bca4ce8dd8ab88ebda2dedb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#ae8f262322bca4ce8dd8ab88ebda2dedb">XDMAPCIE_REGION_EN</a>&#160;&#160;&#160;0x90000000</td></tr>
<tr class="memdesc:ae8f262322bca4ce8dd8ab88ebda2dedb"><td class="mdescLeft">&#160;</td><td class="mdescRight">EN for IATU Address Transalation.  <a href="#ae8f262322bca4ce8dd8ab88ebda2dedb">More...</a><br/></td></tr>
<tr class="separator:ae8f262322bca4ce8dd8ab88ebda2dedb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">IATU Registers</div></td></tr>
<tr class="memitem:acdd10dcc061e19b4fc59bae614d5d623"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#acdd10dcc061e19b4fc59bae614d5d623">XDMAPCIE_ATU_LIMIT_ADDR</a>&#160;&#160;&#160;0xFFFFFF</td></tr>
<tr class="memdesc:acdd10dcc061e19b4fc59bae614d5d623"><td class="mdescLeft">&#160;</td><td class="mdescRight">IATU Limit Address Range.  <a href="#acdd10dcc061e19b4fc59bae614d5d623">More...</a><br/></td></tr>
<tr class="separator:acdd10dcc061e19b4fc59bae614d5d623"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adb19a64b3049aecfb96ecbfaabb0ec4f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#adb19a64b3049aecfb96ecbfaabb0ec4f">XDMAPCIE_ATU_REGION_SIZE</a>&#160;&#160;&#160;0x1000</td></tr>
<tr class="memdesc:adb19a64b3049aecfb96ecbfaabb0ec4f"><td class="mdescLeft">&#160;</td><td class="mdescRight">IATU MAX Region Size.  <a href="#adb19a64b3049aecfb96ecbfaabb0ec4f">More...</a><br/></td></tr>
<tr class="separator:adb19a64b3049aecfb96ecbfaabb0ec4f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">VSECC Register bitmaps and masks</div></td></tr>
<tr class="memitem:a405f9e3195f36f58bd6685bba2231ffb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a405f9e3195f36f58bd6685bba2231ffb">XDMAPCIE_VSECC_ID_MASK</a>&#160;&#160;&#160;0x0000FFFF</td></tr>
<tr class="memdesc:a405f9e3195f36f58bd6685bba2231ffb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Vsec capability Id.  <a href="#a405f9e3195f36f58bd6685bba2231ffb">More...</a><br/></td></tr>
<tr class="separator:a405f9e3195f36f58bd6685bba2231ffb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a34df2e3887910bf3d736e98a983dcdbf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a34df2e3887910bf3d736e98a983dcdbf">XDMAPCIE_VSECC_VER_MASK</a>&#160;&#160;&#160;0x000F0000</td></tr>
<tr class="memdesc:a34df2e3887910bf3d736e98a983dcdbf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Version of capability Structure.  <a href="#a34df2e3887910bf3d736e98a983dcdbf">More...</a><br/></td></tr>
<tr class="separator:a34df2e3887910bf3d736e98a983dcdbf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a848f1c9bd9cdd5b2b9100f46b7353edb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a848f1c9bd9cdd5b2b9100f46b7353edb">XDMAPCIE_VSECC_NEXT_MASK</a>&#160;&#160;&#160;0xFFF00000</td></tr>
<tr class="memdesc:a848f1c9bd9cdd5b2b9100f46b7353edb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset to next capability.  <a href="#a848f1c9bd9cdd5b2b9100f46b7353edb">More...</a><br/></td></tr>
<tr class="separator:a848f1c9bd9cdd5b2b9100f46b7353edb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a019c307ea457a54fe5cffb84f4f807bd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a019c307ea457a54fe5cffb84f4f807bd">XDMAPCIE_VSECC_VER_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:a019c307ea457a54fe5cffb84f4f807bd"><td class="mdescLeft">&#160;</td><td class="mdescRight">VSEC Version shift.  <a href="#a019c307ea457a54fe5cffb84f4f807bd">More...</a><br/></td></tr>
<tr class="separator:a019c307ea457a54fe5cffb84f4f807bd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9e335708c508110cad0e5c36cacb9eac"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a9e335708c508110cad0e5c36cacb9eac">XDMAPCIE_VSECC_NEXT_SHIFT</a>&#160;&#160;&#160;20</td></tr>
<tr class="memdesc:a9e335708c508110cad0e5c36cacb9eac"><td class="mdescLeft">&#160;</td><td class="mdescRight">Next capability offset shift.  <a href="#a9e335708c508110cad0e5c36cacb9eac">More...</a><br/></td></tr>
<tr class="separator:a9e335708c508110cad0e5c36cacb9eac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">VSECH Register bitmaps and masks</div></td></tr>
<tr class="memitem:ad729068100112d67c4a08830e6a12b4d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#ad729068100112d67c4a08830e6a12b4d">XDMAPCIE_VSECH_ID_MASK</a>&#160;&#160;&#160;0x0000FFFF</td></tr>
<tr class="memdesc:ad729068100112d67c4a08830e6a12b4d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Vsec structure Id.  <a href="#ad729068100112d67c4a08830e6a12b4d">More...</a><br/></td></tr>
<tr class="separator:ad729068100112d67c4a08830e6a12b4d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a29d0c0b9219248958c08a5a557b01309"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a29d0c0b9219248958c08a5a557b01309">XDMAPCIE_VSECH_REV_MASK</a>&#160;&#160;&#160;0x000F0000</td></tr>
<tr class="memdesc:a29d0c0b9219248958c08a5a557b01309"><td class="mdescLeft">&#160;</td><td class="mdescRight">Vsec header version.  <a href="#a29d0c0b9219248958c08a5a557b01309">More...</a><br/></td></tr>
<tr class="separator:a29d0c0b9219248958c08a5a557b01309"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1471191e3dbfee9c528d5c42a1f6691f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a1471191e3dbfee9c528d5c42a1f6691f">XDMAPCIE_VSECH_LEN_MASK</a>&#160;&#160;&#160;0xFFF00000</td></tr>
<tr class="memdesc:a1471191e3dbfee9c528d5c42a1f6691f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Length of Vsec capability structure.  <a href="#a1471191e3dbfee9c528d5c42a1f6691f">More...</a><br/></td></tr>
<tr class="separator:a1471191e3dbfee9c528d5c42a1f6691f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a45941794e0251d660ceb5b2ff390155a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a45941794e0251d660ceb5b2ff390155a">XDMAPCIE_VSECH_REV_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:a45941794e0251d660ceb5b2ff390155a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Vsec version shift.  <a href="#a45941794e0251d660ceb5b2ff390155a">More...</a><br/></td></tr>
<tr class="separator:a45941794e0251d660ceb5b2ff390155a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a324566449eb7d1f827007b13f8c3c127"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a324566449eb7d1f827007b13f8c3c127">XDMAPCIE_VSECH_LEN_SHIFT</a>&#160;&#160;&#160;20</td></tr>
<tr class="memdesc:a324566449eb7d1f827007b13f8c3c127"><td class="mdescLeft">&#160;</td><td class="mdescRight">Vsec length shift.  <a href="#a324566449eb7d1f827007b13f8c3c127">More...</a><br/></td></tr>
<tr class="separator:a324566449eb7d1f827007b13f8c3c127"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bridge Info Register bitmaps and masks</div></td></tr>
<tr class="memitem:a2799a39816b787225defc73fb71b174a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a2799a39816b787225defc73fb71b174a">XDMAPCIE_BI_GEN2_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:a2799a39816b787225defc73fb71b174a"><td class="mdescLeft">&#160;</td><td class="mdescRight">PCIe Gen2 Speed Support Mask.  <a href="#a2799a39816b787225defc73fb71b174a">More...</a><br/></td></tr>
<tr class="separator:a2799a39816b787225defc73fb71b174a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1341b82af3253d651248943c9c106b85"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a1341b82af3253d651248943c9c106b85">XDMAPCIE_BI_RP_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:a1341b82af3253d651248943c9c106b85"><td class="mdescLeft">&#160;</td><td class="mdescRight">PCIe Root Port Support.  <a href="#a1341b82af3253d651248943c9c106b85">More...</a><br/></td></tr>
<tr class="separator:a1341b82af3253d651248943c9c106b85"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a77a6fe6cbb4114298960a620f0e6f7a3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a77a6fe6cbb4114298960a620f0e6f7a3">XDMAPCIE_UP_CONFIG_CAPABLE</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:a77a6fe6cbb4114298960a620f0e6f7a3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Up Config Capable.  <a href="#a77a6fe6cbb4114298960a620f0e6f7a3">More...</a><br/></td></tr>
<tr class="separator:a77a6fe6cbb4114298960a620f0e6f7a3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abcda754d0a61c43d447fadb67aaa7434"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#abcda754d0a61c43d447fadb67aaa7434">XDMAPCIE_BI_ECAM_SIZE_MASK</a>&#160;&#160;&#160;0x00070000</td></tr>
<tr class="memdesc:abcda754d0a61c43d447fadb67aaa7434"><td class="mdescLeft">&#160;</td><td class="mdescRight">ECAM size.  <a href="#abcda754d0a61c43d447fadb67aaa7434">More...</a><br/></td></tr>
<tr class="separator:abcda754d0a61c43d447fadb67aaa7434"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae4893d95f81629e3f530ac3f469865ec"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#ae4893d95f81629e3f530ac3f469865ec">XDMAPCIE_BI_RP_SHIFT</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:ae4893d95f81629e3f530ac3f469865ec"><td class="mdescLeft">&#160;</td><td class="mdescRight">PCIe Root Port Shift.  <a href="#ae4893d95f81629e3f530ac3f469865ec">More...</a><br/></td></tr>
<tr class="separator:ae4893d95f81629e3f530ac3f469865ec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4a8456b90f69f3ca2c3a8db12ea24ee8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a4a8456b90f69f3ca2c3a8db12ea24ee8">XDMAPCIE_BI_ECAM_SIZE_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:a4a8456b90f69f3ca2c3a8db12ea24ee8"><td class="mdescLeft">&#160;</td><td class="mdescRight">PCIe ECAM Size Shift.  <a href="#a4a8456b90f69f3ca2c3a8db12ea24ee8">More...</a><br/></td></tr>
<tr class="separator:a4a8456b90f69f3ca2c3a8db12ea24ee8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bridge Status &amp; Control Register bitmaps and masks</div></td></tr>
<tr class="memitem:a0728df5057cc9ea9a5042242192a59cf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a0728df5057cc9ea9a5042242192a59cf">XDMAPCIE_BSC_ECAM_BUSY_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:a0728df5057cc9ea9a5042242192a59cf"><td class="mdescLeft">&#160;</td><td class="mdescRight">ECAM Busy Status.  <a href="#a0728df5057cc9ea9a5042242192a59cf">More...</a><br/></td></tr>
<tr class="separator:a0728df5057cc9ea9a5042242192a59cf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad1ca428956c846fb789bc4c9bb31bc58"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#ad1ca428956c846fb789bc4c9bb31bc58">XDMAPCIE_BSC_GI_MASK</a>&#160;&#160;&#160;0x00000100</td></tr>
<tr class="memdesc:ad1ca428956c846fb789bc4c9bb31bc58"><td class="mdescLeft">&#160;</td><td class="mdescRight">Global Interrupt Disable.  <a href="#ad1ca428956c846fb789bc4c9bb31bc58">More...</a><br/></td></tr>
<tr class="separator:ad1ca428956c846fb789bc4c9bb31bc58"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4823f914daacc6021a06d7784339f310"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a4823f914daacc6021a06d7784339f310">XDMAPCIE_BSC_RW1C_MASK</a>&#160;&#160;&#160;0x00010000</td></tr>
<tr class="memdesc:a4823f914daacc6021a06d7784339f310"><td class="mdescLeft">&#160;</td><td class="mdescRight">RW Permissions to RW1C Registers.  <a href="#a4823f914daacc6021a06d7784339f310">More...</a><br/></td></tr>
<tr class="separator:a4823f914daacc6021a06d7784339f310"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7b6e2b54068968f298376377cbc33176"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a7b6e2b54068968f298376377cbc33176">XDMAPCIE_BSC_RO_MASK</a>&#160;&#160;&#160;0x00020000</td></tr>
<tr class="memdesc:a7b6e2b54068968f298376377cbc33176"><td class="mdescLeft">&#160;</td><td class="mdescRight">RW Permissions to RO Registers.  <a href="#a7b6e2b54068968f298376377cbc33176">More...</a><br/></td></tr>
<tr class="separator:a7b6e2b54068968f298376377cbc33176"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a46af7762c004cff0605f71238f33039a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a46af7762c004cff0605f71238f33039a">XDMAPCIE_BSC_GI_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:a46af7762c004cff0605f71238f33039a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Global Interrupt Disable Shift.  <a href="#a46af7762c004cff0605f71238f33039a">More...</a><br/></td></tr>
<tr class="separator:a46af7762c004cff0605f71238f33039a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2b1ce6f833d863b5d57787f4128ae155"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a2b1ce6f833d863b5d57787f4128ae155">XDMAPCIE_BSC_RW1C_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:a2b1ce6f833d863b5d57787f4128ae155"><td class="mdescLeft">&#160;</td><td class="mdescRight">RW1C Shift.  <a href="#a2b1ce6f833d863b5d57787f4128ae155">More...</a><br/></td></tr>
<tr class="separator:a2b1ce6f833d863b5d57787f4128ae155"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0b003ed96b00faaaece734e463b82f7c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a0b003ed96b00faaaece734e463b82f7c">XDMAPCIE_BSC_RO_SHIFT</a>&#160;&#160;&#160;17</td></tr>
<tr class="memdesc:a0b003ed96b00faaaece734e463b82f7c"><td class="mdescLeft">&#160;</td><td class="mdescRight">RO as RW Shift.  <a href="#a0b003ed96b00faaaece734e463b82f7c">More...</a><br/></td></tr>
<tr class="separator:a0b003ed96b00faaaece734e463b82f7c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Interrupt Decode Register bitmaps and masks</div></td></tr>
<tr class="memitem:a6393e69d63266d198bbd282fed4d1e97"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a6393e69d63266d198bbd282fed4d1e97">XDMAPCIE_ID_LINK_DOWN_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:a6393e69d63266d198bbd282fed4d1e97"><td class="mdescLeft">&#160;</td><td class="mdescRight">Link Down Mask.  <a href="#a6393e69d63266d198bbd282fed4d1e97">More...</a><br/></td></tr>
<tr class="separator:a6393e69d63266d198bbd282fed4d1e97"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a13b93ab0b7d234ac97041dc2db299290"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a13b93ab0b7d234ac97041dc2db299290">XDMAPCIE_ID_ECRC_ERR_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:a13b93ab0b7d234ac97041dc2db299290"><td class="mdescLeft">&#160;</td><td class="mdescRight">Rx Packet CRC failed.  <a href="#a13b93ab0b7d234ac97041dc2db299290">More...</a><br/></td></tr>
<tr class="separator:a13b93ab0b7d234ac97041dc2db299290"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae68bc7f69def3b43c55de8b3b2bac667"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#ae68bc7f69def3b43c55de8b3b2bac667">XDMAPCIE_ID_STR_ERR_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ae68bc7f69def3b43c55de8b3b2bac667"><td class="mdescLeft">&#160;</td><td class="mdescRight">Streaming Error Mask.  <a href="#ae68bc7f69def3b43c55de8b3b2bac667">More...</a><br/></td></tr>
<tr class="separator:ae68bc7f69def3b43c55de8b3b2bac667"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af1702905586d6770aa2222bf528953f7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#af1702905586d6770aa2222bf528953f7">XDMAPCIE_ID_HOT_RST_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:af1702905586d6770aa2222bf528953f7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Hot Reset Mask.  <a href="#af1702905586d6770aa2222bf528953f7">More...</a><br/></td></tr>
<tr class="separator:af1702905586d6770aa2222bf528953f7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac5bccd0f9b46204220d8d51aa94bd551"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#ac5bccd0f9b46204220d8d51aa94bd551">XDMAPCIE_ID_CFG_COMPL_STATE_MASK</a>&#160;&#160;&#160;0x000000E0</td></tr>
<tr class="memdesc:ac5bccd0f9b46204220d8d51aa94bd551"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cfg Completion Status Mask.  <a href="#ac5bccd0f9b46204220d8d51aa94bd551">More...</a><br/></td></tr>
<tr class="separator:ac5bccd0f9b46204220d8d51aa94bd551"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa3898ed9e90c9e23f9315693062a3991"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#aa3898ed9e90c9e23f9315693062a3991">XDMAPCIE_ID_CFG_TIMEOUT_MASK</a>&#160;&#160;&#160;0x00000100</td></tr>
<tr class="memdesc:aa3898ed9e90c9e23f9315693062a3991"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cfg timeout Mask.  <a href="#aa3898ed9e90c9e23f9315693062a3991">More...</a><br/></td></tr>
<tr class="separator:aa3898ed9e90c9e23f9315693062a3991"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acb23423c511b625fdeeb7e43bb045c27"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#acb23423c511b625fdeeb7e43bb045c27">XDMAPCIE_ID_CORRECTABLE_ERR_MASK</a>&#160;&#160;&#160;0x00000200</td></tr>
<tr class="memdesc:acb23423c511b625fdeeb7e43bb045c27"><td class="mdescLeft">&#160;</td><td class="mdescRight">Correctable Error Mask.  <a href="#acb23423c511b625fdeeb7e43bb045c27">More...</a><br/></td></tr>
<tr class="separator:acb23423c511b625fdeeb7e43bb045c27"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9e758cb476b717c4d7e6a2d887eb6f3d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a9e758cb476b717c4d7e6a2d887eb6f3d">XDMAPCIE_ID_NONFATAL_ERR_MASK</a>&#160;&#160;&#160;0x00000400</td></tr>
<tr class="memdesc:a9e758cb476b717c4d7e6a2d887eb6f3d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Non-Fatal Error Mask.  <a href="#a9e758cb476b717c4d7e6a2d887eb6f3d">More...</a><br/></td></tr>
<tr class="separator:a9e758cb476b717c4d7e6a2d887eb6f3d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a34952b92fd0bdec7cae59ffce16e83e8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a34952b92fd0bdec7cae59ffce16e83e8">XDMAPCIE_ID_FATAL_ERR_MASK</a>&#160;&#160;&#160;0x00000800</td></tr>
<tr class="memdesc:a34952b92fd0bdec7cae59ffce16e83e8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Fatal Error Mask.  <a href="#a34952b92fd0bdec7cae59ffce16e83e8">More...</a><br/></td></tr>
<tr class="separator:a34952b92fd0bdec7cae59ffce16e83e8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adb47b94222ead79c34bfe67cb6666ba9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#adb47b94222ead79c34bfe67cb6666ba9">XDMAPCIE_ID_INTX_INTERRUPT</a>&#160;&#160;&#160;0x00010000</td></tr>
<tr class="memdesc:adb47b94222ead79c34bfe67cb6666ba9"><td class="mdescLeft">&#160;</td><td class="mdescRight">INTX Interrupt.  <a href="#adb47b94222ead79c34bfe67cb6666ba9">More...</a><br/></td></tr>
<tr class="separator:adb47b94222ead79c34bfe67cb6666ba9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aeec993ac36af4e9a89c5a0d7f7c8cbed"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#aeec993ac36af4e9a89c5a0d7f7c8cbed">XDMAPCIE_ID_MSI_INTERRUPT</a>&#160;&#160;&#160;0x00020000</td></tr>
<tr class="memdesc:aeec993ac36af4e9a89c5a0d7f7c8cbed"><td class="mdescLeft">&#160;</td><td class="mdescRight">MSI Interrupt.  <a href="#aeec993ac36af4e9a89c5a0d7f7c8cbed">More...</a><br/></td></tr>
<tr class="separator:aeec993ac36af4e9a89c5a0d7f7c8cbed"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abb39a730f4774f13c67530fde1d5047e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#abb39a730f4774f13c67530fde1d5047e">XDMAPCIE_ID_UNSUPP_CMPL_MASK</a>&#160;&#160;&#160;0x00100000</td></tr>
<tr class="memdesc:abb39a730f4774f13c67530fde1d5047e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave Unsupported Request Mask.  <a href="#abb39a730f4774f13c67530fde1d5047e">More...</a><br/></td></tr>
<tr class="separator:abb39a730f4774f13c67530fde1d5047e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7853190498c4f53cdfd68b584f99f082"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a7853190498c4f53cdfd68b584f99f082">XDMAPCIE_ID_UNEXP_CMPL_MASK</a>&#160;&#160;&#160;0x00200000</td></tr>
<tr class="memdesc:a7853190498c4f53cdfd68b584f99f082"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave Unexpected Completion Mask.  <a href="#a7853190498c4f53cdfd68b584f99f082">More...</a><br/></td></tr>
<tr class="separator:a7853190498c4f53cdfd68b584f99f082"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3b34e886cec2892554cbf31cc08c9197"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a3b34e886cec2892554cbf31cc08c9197">XDMAPCIE_ID_CMPL_TIMEOUT_MASK</a>&#160;&#160;&#160;0x00400000</td></tr>
<tr class="memdesc:a3b34e886cec2892554cbf31cc08c9197"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave completion Time Mask.  <a href="#a3b34e886cec2892554cbf31cc08c9197">More...</a><br/></td></tr>
<tr class="separator:a3b34e886cec2892554cbf31cc08c9197"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1a81495ce39f05d61fb1317b4bf4f739"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a1a81495ce39f05d61fb1317b4bf4f739">XDMAPCIE_ID_SLV_EP_MASK</a>&#160;&#160;&#160;0x00800000</td></tr>
<tr class="memdesc:a1a81495ce39f05d61fb1317b4bf4f739"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave Error Poison Mask.  <a href="#a1a81495ce39f05d61fb1317b4bf4f739">More...</a><br/></td></tr>
<tr class="separator:a1a81495ce39f05d61fb1317b4bf4f739"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afe136278e0354b9ba85ba73226ce9e23"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#afe136278e0354b9ba85ba73226ce9e23">XDMAPCIE_ID_CMPL_ABT_MASK</a>&#160;&#160;&#160;0x01000000</td></tr>
<tr class="memdesc:afe136278e0354b9ba85ba73226ce9e23"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave completion Abort Mask.  <a href="#afe136278e0354b9ba85ba73226ce9e23">More...</a><br/></td></tr>
<tr class="separator:afe136278e0354b9ba85ba73226ce9e23"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae55e7ffef0ef619cd1ba62f0e7f6551d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#ae55e7ffef0ef619cd1ba62f0e7f6551d">XDMAPCIE_ID_ILL_BURST_MASK</a>&#160;&#160;&#160;0x02000000</td></tr>
<tr class="memdesc:ae55e7ffef0ef619cd1ba62f0e7f6551d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave Illegal Burst Mask.  <a href="#ae55e7ffef0ef619cd1ba62f0e7f6551d">More...</a><br/></td></tr>
<tr class="separator:ae55e7ffef0ef619cd1ba62f0e7f6551d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a12b13b8b5223de6bc6df7447ab6d3a68"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a12b13b8b5223de6bc6df7447ab6d3a68">XDMAPCIE_ID_DECODE_ERR_MASK</a>&#160;&#160;&#160;0x04000000</td></tr>
<tr class="memdesc:a12b13b8b5223de6bc6df7447ab6d3a68"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master Decode Error Interrupt Mask.  <a href="#a12b13b8b5223de6bc6df7447ab6d3a68">More...</a><br/></td></tr>
<tr class="separator:a12b13b8b5223de6bc6df7447ab6d3a68"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad8c3856f42ac333491d841cfabf27907"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#ad8c3856f42ac333491d841cfabf27907">XDMAPCIE_ID_SLAVE_ERR_MASK</a>&#160;&#160;&#160;0x08000000</td></tr>
<tr class="memdesc:ad8c3856f42ac333491d841cfabf27907"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master Slave Error Interrupt Mask.  <a href="#ad8c3856f42ac333491d841cfabf27907">More...</a><br/></td></tr>
<tr class="separator:ad8c3856f42ac333491d841cfabf27907"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aea347b3278e7f818123e606172331b2a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#aea347b3278e7f818123e606172331b2a">XDMAPCIE_ID_MASTER_EP_MASK</a>&#160;&#160;&#160;0x10000000</td></tr>
<tr class="memdesc:aea347b3278e7f818123e606172331b2a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master Error Poison Mask.  <a href="#aea347b3278e7f818123e606172331b2a">More...</a><br/></td></tr>
<tr class="separator:aea347b3278e7f818123e606172331b2a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a74b7f78c8f8f27be92d422ccfb084e07"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a74b7f78c8f8f27be92d422ccfb084e07">XDMAPCIE_ID_CLEAR_ALL_MASK</a>&#160;&#160;&#160;0xFFFFFFFF</td></tr>
<tr class="memdesc:a74b7f78c8f8f27be92d422ccfb084e07"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mask of all Interrupts.  <a href="#a74b7f78c8f8f27be92d422ccfb084e07">More...</a><br/></td></tr>
<tr class="separator:a74b7f78c8f8f27be92d422ccfb084e07"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Interrupt Mask Register bitmaps and masks</div></td></tr>
<tr class="memitem:ab18aeb506ecb660c694912cb6935c096"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#ab18aeb506ecb660c694912cb6935c096">XDMAPCIE_IM_ENABLE_ALL_MASK</a>&#160;&#160;&#160;0xFFFFFFFF</td></tr>
<tr class="memdesc:ab18aeb506ecb660c694912cb6935c096"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable All Interrupts.  <a href="#ab18aeb506ecb660c694912cb6935c096">More...</a><br/></td></tr>
<tr class="separator:ab18aeb506ecb660c694912cb6935c096"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a41b00f72c89e54b044acfcd7bb7dfc86"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a41b00f72c89e54b044acfcd7bb7dfc86">XDMAPCIE_IM_DISABLE_ALL_MASK</a>&#160;&#160;&#160;0x00000000</td></tr>
<tr class="memdesc:a41b00f72c89e54b044acfcd7bb7dfc86"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable All Interrupts.  <a href="#a41b00f72c89e54b044acfcd7bb7dfc86">More...</a><br/></td></tr>
<tr class="separator:a41b00f72c89e54b044acfcd7bb7dfc86"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bus Location Register bitmaps and masks</div></td></tr>
<tr class="memitem:af5b647370bc05fa2a455f1569f7d5ef7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#af5b647370bc05fa2a455f1569f7d5ef7">XDMAPCIE_BL_FUNC_MASK</a>&#160;&#160;&#160;0x00000007</td></tr>
<tr class="memdesc:af5b647370bc05fa2a455f1569f7d5ef7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Requester ID Function Number.  <a href="#af5b647370bc05fa2a455f1569f7d5ef7">More...</a><br/></td></tr>
<tr class="separator:af5b647370bc05fa2a455f1569f7d5ef7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2b76774fe73eb5ddac64acd04d18a8f2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a2b76774fe73eb5ddac64acd04d18a8f2">XDMAPCIE_BL_DEV_MASK</a>&#160;&#160;&#160;0x000000F8</td></tr>
<tr class="memdesc:a2b76774fe73eb5ddac64acd04d18a8f2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Requester ID Device Number.  <a href="#a2b76774fe73eb5ddac64acd04d18a8f2">More...</a><br/></td></tr>
<tr class="separator:a2b76774fe73eb5ddac64acd04d18a8f2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac59090cdcbe3d2156f27165a33e21d3c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#ac59090cdcbe3d2156f27165a33e21d3c">XDMAPCIE_BL_BUS_MASK</a>&#160;&#160;&#160;0x0000FF00</td></tr>
<tr class="memdesc:ac59090cdcbe3d2156f27165a33e21d3c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Requester ID Bus Number.  <a href="#ac59090cdcbe3d2156f27165a33e21d3c">More...</a><br/></td></tr>
<tr class="separator:ac59090cdcbe3d2156f27165a33e21d3c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acf6e6d7e43697c4b98bbf6f645f901dd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#acf6e6d7e43697c4b98bbf6f645f901dd">XDMAPCIE_BL_PORT_MASK</a>&#160;&#160;&#160;0x00FF0000</td></tr>
<tr class="memdesc:acf6e6d7e43697c4b98bbf6f645f901dd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Requester ID Port Number.  <a href="#acf6e6d7e43697c4b98bbf6f645f901dd">More...</a><br/></td></tr>
<tr class="separator:acf6e6d7e43697c4b98bbf6f645f901dd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a77a9c17fea6e28f4daa1a40b933d38e0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a77a9c17fea6e28f4daa1a40b933d38e0">XDMAPCIE_BL_DEV_SHIFT</a>&#160;&#160;&#160;3</td></tr>
<tr class="memdesc:a77a9c17fea6e28f4daa1a40b933d38e0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Requester ID Device Number Shift Value.  <a href="#a77a9c17fea6e28f4daa1a40b933d38e0">More...</a><br/></td></tr>
<tr class="separator:a77a9c17fea6e28f4daa1a40b933d38e0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acc86d34d06e7fd42e5289dbc30aa680e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#acc86d34d06e7fd42e5289dbc30aa680e">XDMAPCIE_BL_BUS_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:acc86d34d06e7fd42e5289dbc30aa680e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Requester ID Bus Number Shift Value.  <a href="#acc86d34d06e7fd42e5289dbc30aa680e">More...</a><br/></td></tr>
<tr class="separator:acc86d34d06e7fd42e5289dbc30aa680e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac94b2bf9a1b1abfccc5c67b8e2fed743"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#ac94b2bf9a1b1abfccc5c67b8e2fed743">XDMAPCIE_BL_PORT_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ac94b2bf9a1b1abfccc5c67b8e2fed743"><td class="mdescLeft">&#160;</td><td class="mdescRight">Requester ID Bus Number Shift Value.  <a href="#ac94b2bf9a1b1abfccc5c67b8e2fed743">More...</a><br/></td></tr>
<tr class="separator:ac94b2bf9a1b1abfccc5c67b8e2fed743"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">PHY Status &amp; Control Register bitmaps and masks</div></td></tr>
<tr class="memitem:aead4ac7cb9705e7cf69aa71f9b3fbaf4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#aead4ac7cb9705e7cf69aa71f9b3fbaf4">XDMAPCIE_PHYSC_LINK_RATE_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:aead4ac7cb9705e7cf69aa71f9b3fbaf4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Link Rate.  <a href="#aead4ac7cb9705e7cf69aa71f9b3fbaf4">More...</a><br/></td></tr>
<tr class="separator:aead4ac7cb9705e7cf69aa71f9b3fbaf4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a190170032f01cf924d9c5fb21364ae2c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a190170032f01cf924d9c5fb21364ae2c">XDMAPCIE_PHYSC_LINK_WIDTH_MASK</a>&#160;&#160;&#160;0x00000006</td></tr>
<tr class="memdesc:a190170032f01cf924d9c5fb21364ae2c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Link Width Mask.  <a href="#a190170032f01cf924d9c5fb21364ae2c">More...</a><br/></td></tr>
<tr class="separator:a190170032f01cf924d9c5fb21364ae2c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a11060b116fe77cdcde667e7e40297356"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a11060b116fe77cdcde667e7e40297356">XDMAPCIE_PHYSC_LTSSM_STATE_MASK</a>&#160;&#160;&#160;0x000001F8</td></tr>
<tr class="memdesc:a11060b116fe77cdcde667e7e40297356"><td class="mdescLeft">&#160;</td><td class="mdescRight">LTSSM State Mask.  <a href="#a11060b116fe77cdcde667e7e40297356">More...</a><br/></td></tr>
<tr class="separator:a11060b116fe77cdcde667e7e40297356"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a515854000c3f9bc56e9f587d68cb4af8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a515854000c3f9bc56e9f587d68cb4af8">XDMAPCIE_PHYSC_LANE_REV_MASK</a>&#160;&#160;&#160;0x00000600</td></tr>
<tr class="memdesc:a515854000c3f9bc56e9f587d68cb4af8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Lane Reversal Mask.  <a href="#a515854000c3f9bc56e9f587d68cb4af8">More...</a><br/></td></tr>
<tr class="separator:a515854000c3f9bc56e9f587d68cb4af8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afc16fa2f0ab33302ebf077134d3b7047"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#afc16fa2f0ab33302ebf077134d3b7047">XDMAPCIE_PHYSC_LINK_UP_MASK</a>&#160;&#160;&#160;0x00000800</td></tr>
<tr class="memdesc:afc16fa2f0ab33302ebf077134d3b7047"><td class="mdescLeft">&#160;</td><td class="mdescRight">Link Up Status Mask.  <a href="#afc16fa2f0ab33302ebf077134d3b7047">More...</a><br/></td></tr>
<tr class="separator:afc16fa2f0ab33302ebf077134d3b7047"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a98d409214ea974e741462c5d0554ff04"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a98d409214ea974e741462c5d0554ff04">XDMAPCIE_PHYSC_DLW_MASK</a>&#160;&#160;&#160;0x00030000</td></tr>
<tr class="memdesc:a98d409214ea974e741462c5d0554ff04"><td class="mdescLeft">&#160;</td><td class="mdescRight">Directed Link Width to change Mask.  <a href="#a98d409214ea974e741462c5d0554ff04">More...</a><br/></td></tr>
<tr class="separator:a98d409214ea974e741462c5d0554ff04"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a725a5843208630c43a47984e91e6abcc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a725a5843208630c43a47984e91e6abcc">XDMAPCIE_PHYSC_DLWS_MASK</a>&#160;&#160;&#160;0x00040000</td></tr>
<tr class="memdesc:a725a5843208630c43a47984e91e6abcc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Directed Link Width Speed to change Mask.  <a href="#a725a5843208630c43a47984e91e6abcc">More...</a><br/></td></tr>
<tr class="separator:a725a5843208630c43a47984e91e6abcc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a07918f0976ea05b659dcb48830024b94"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a07918f0976ea05b659dcb48830024b94">XDMAPCIE_PHYSC_DLA_MASK</a>&#160;&#160;&#160;0x00080000</td></tr>
<tr class="memdesc:a07918f0976ea05b659dcb48830024b94"><td class="mdescLeft">&#160;</td><td class="mdescRight">Directed Link Change change to reliability or Autonomus Mask.  <a href="#a07918f0976ea05b659dcb48830024b94">More...</a><br/></td></tr>
<tr class="separator:a07918f0976ea05b659dcb48830024b94"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad0e15c8e4792b8fe09d23371bc640d7d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#ad0e15c8e4792b8fe09d23371bc640d7d">XDMAPCIE_PHYSC_DLC_MASK</a>&#160;&#160;&#160;0x00300000</td></tr>
<tr class="memdesc:ad0e15c8e4792b8fe09d23371bc640d7d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Directed Link change Mask.  <a href="#ad0e15c8e4792b8fe09d23371bc640d7d">More...</a><br/></td></tr>
<tr class="separator:ad0e15c8e4792b8fe09d23371bc640d7d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad95083dc0eab75d131ae07bea00232b3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#ad95083dc0eab75d131ae07bea00232b3">XDMAPCIE_PHYSC_LINK_WIDTH_SHIFT</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:ad95083dc0eab75d131ae07bea00232b3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Link Status Shift.  <a href="#ad95083dc0eab75d131ae07bea00232b3">More...</a><br/></td></tr>
<tr class="separator:ad95083dc0eab75d131ae07bea00232b3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a68853d48944ae42e9a42d2812fb58ae8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a68853d48944ae42e9a42d2812fb58ae8">XDMAPCIE_PHYSC_LTSSM_STATE_SHIFT</a>&#160;&#160;&#160;3</td></tr>
<tr class="memdesc:a68853d48944ae42e9a42d2812fb58ae8"><td class="mdescLeft">&#160;</td><td class="mdescRight">LTSSM State Shift.  <a href="#a68853d48944ae42e9a42d2812fb58ae8">More...</a><br/></td></tr>
<tr class="separator:a68853d48944ae42e9a42d2812fb58ae8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad6de7d11a8a2ad86e322589d12eacae9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#ad6de7d11a8a2ad86e322589d12eacae9">XDMAPCIE_PHYSC_LANE_REV_SHIFT</a>&#160;&#160;&#160;9</td></tr>
<tr class="memdesc:ad6de7d11a8a2ad86e322589d12eacae9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Lane Reversal Shift.  <a href="#ad6de7d11a8a2ad86e322589d12eacae9">More...</a><br/></td></tr>
<tr class="separator:ad6de7d11a8a2ad86e322589d12eacae9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a55c53bb702906f82360a637c3432e0f8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a55c53bb702906f82360a637c3432e0f8">XDMAPCIE_PHYSC_LINK_UP_SHIFT</a>&#160;&#160;&#160;11</td></tr>
<tr class="memdesc:a55c53bb702906f82360a637c3432e0f8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Link Up Status Shift.  <a href="#a55c53bb702906f82360a637c3432e0f8">More...</a><br/></td></tr>
<tr class="separator:a55c53bb702906f82360a637c3432e0f8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab5c738000b50589ca980af8b05060f2a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#ab5c738000b50589ca980af8b05060f2a">XDMAPCIE_PHYSC_DLW_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ab5c738000b50589ca980af8b05060f2a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Directed Link Width to change Shift.  <a href="#ab5c738000b50589ca980af8b05060f2a">More...</a><br/></td></tr>
<tr class="separator:ab5c738000b50589ca980af8b05060f2a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a92f25d869be109d6d65ead06dfb95ced"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a92f25d869be109d6d65ead06dfb95ced">XDMAPCIE_PHYSC_DLWS_SHIFT</a>&#160;&#160;&#160;18</td></tr>
<tr class="memdesc:a92f25d869be109d6d65ead06dfb95ced"><td class="mdescLeft">&#160;</td><td class="mdescRight">Directed Link Width Speed to change Shift.  <a href="#a92f25d869be109d6d65ead06dfb95ced">More...</a><br/></td></tr>
<tr class="separator:a92f25d869be109d6d65ead06dfb95ced"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae47139cb2b379d4bff359036aa42abe1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#ae47139cb2b379d4bff359036aa42abe1">XDMAPCIE_PHYSC_DLA_SHIFT</a>&#160;&#160;&#160;19</td></tr>
<tr class="memdesc:ae47139cb2b379d4bff359036aa42abe1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Directed Link change to reliability or Autonomus Shift.  <a href="#ae47139cb2b379d4bff359036aa42abe1">More...</a><br/></td></tr>
<tr class="separator:ae47139cb2b379d4bff359036aa42abe1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aaedcc562b141445a3e3d1ff902b0f181"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#aaedcc562b141445a3e3d1ff902b0f181">XDMAPCIE_PHYSC_DLC_SHIFT</a>&#160;&#160;&#160;20</td></tr>
<tr class="memdesc:aaedcc562b141445a3e3d1ff902b0f181"><td class="mdescLeft">&#160;</td><td class="mdescRight">Directed Link change Shift.  <a href="#aaedcc562b141445a3e3d1ff902b0f181">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Root Port Status/Control Register bitmaps and masks</div></td></tr>
<tr class="memitem:a8e480ce2a44fd9f14991d2421c4db0c7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a8e480ce2a44fd9f14991d2421c4db0c7">XDMAPCIE_RPSC_MASK</a>&#160;&#160;&#160;0x0FFF0001</td></tr>
<tr class="memdesc:a8e480ce2a44fd9f14991d2421c4db0c7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Register mask.  <a href="#a8e480ce2a44fd9f14991d2421c4db0c7">More...</a><br/></td></tr>
<tr class="separator:a8e480ce2a44fd9f14991d2421c4db0c7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab96dc6e8195341e32b42ca36f3aec23e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#ab96dc6e8195341e32b42ca36f3aec23e">XDMAPCIE_RPSC_BRIDGE_ENABLE_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ab96dc6e8195341e32b42ca36f3aec23e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bridge Enable Mask.  <a href="#ab96dc6e8195341e32b42ca36f3aec23e">More...</a><br/></td></tr>
<tr class="separator:ab96dc6e8195341e32b42ca36f3aec23e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abffbe554f8cc85db7abbd1cbe2b4dfe8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#abffbe554f8cc85db7abbd1cbe2b4dfe8">XDMAPCIE_RPSC_ERR_FIFO_NOT_EMPTY_MASK</a>&#160;&#160;&#160;0x00010000</td></tr>
<tr class="memdesc:abffbe554f8cc85db7abbd1cbe2b4dfe8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Error FIFO Not Empty.  <a href="#abffbe554f8cc85db7abbd1cbe2b4dfe8">More...</a><br/></td></tr>
<tr class="separator:abffbe554f8cc85db7abbd1cbe2b4dfe8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a678edd87e3e899c48a60c127eb7638ae"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a678edd87e3e899c48a60c127eb7638ae">XDMAPCIE_RPSC_ERR_FIFO_OVERFLOW_MASK</a>&#160;&#160;&#160;0x00020000</td></tr>
<tr class="memdesc:a678edd87e3e899c48a60c127eb7638ae"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Error FIFO Overflow.  <a href="#a678edd87e3e899c48a60c127eb7638ae">More...</a><br/></td></tr>
<tr class="separator:a678edd87e3e899c48a60c127eb7638ae"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7070839d967cea172a8f994a1b518e5b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a7070839d967cea172a8f994a1b518e5b">XDMAPCIE_RPSC_INT_FIFO_NOT_EMPTY_MASK</a>&#160;&#160;&#160;0x00040000</td></tr>
<tr class="memdesc:a7070839d967cea172a8f994a1b518e5b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Interrupt FIFO Not Empty.  <a href="#a7070839d967cea172a8f994a1b518e5b">More...</a><br/></td></tr>
<tr class="separator:a7070839d967cea172a8f994a1b518e5b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a749e43cd6d57f047c7a5484ada878114"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a749e43cd6d57f047c7a5484ada878114">XDMAPCIE_RPSC_INT_FIFO_OVERFLOW_MASK</a>&#160;&#160;&#160;0x00080000</td></tr>
<tr class="memdesc:a749e43cd6d57f047c7a5484ada878114"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Interrupt FIFO Overflow.  <a href="#a749e43cd6d57f047c7a5484ada878114">More...</a><br/></td></tr>
<tr class="separator:a749e43cd6d57f047c7a5484ada878114"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af965b436e06bf4ca8aa3c8cf860ace6b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#af965b436e06bf4ca8aa3c8cf860ace6b">XDMAPCIE_RPSC_COMP_TIMEOUT_MASK</a>&#160;&#160;&#160;0x0FF00000</td></tr>
<tr class="memdesc:af965b436e06bf4ca8aa3c8cf860ace6b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Completion Timeout.  <a href="#af965b436e06bf4ca8aa3c8cf860ace6b">More...</a><br/></td></tr>
<tr class="separator:af965b436e06bf4ca8aa3c8cf860ace6b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abe32d765694043ff1995db28e229b2a9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#abe32d765694043ff1995db28e229b2a9">XDMAPCIE_RPSC_ERR_FIFO_NOT_EMPTY_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:abe32d765694043ff1995db28e229b2a9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Error FIFO Empty Shift.  <a href="#abe32d765694043ff1995db28e229b2a9">More...</a><br/></td></tr>
<tr class="separator:abe32d765694043ff1995db28e229b2a9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9337c811fae2354f9c20c3cd241cf600"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a9337c811fae2354f9c20c3cd241cf600">XDMAPCIE_RPSC_ERR_FIFO_OVERFLOW_SHIFT</a>&#160;&#160;&#160;17</td></tr>
<tr class="memdesc:a9337c811fae2354f9c20c3cd241cf600"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Error FIFO Overflow Shift.  <a href="#a9337c811fae2354f9c20c3cd241cf600">More...</a><br/></td></tr>
<tr class="separator:a9337c811fae2354f9c20c3cd241cf600"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5bb602a109560d8ef2a81760aaf6c0d0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a5bb602a109560d8ef2a81760aaf6c0d0">XDMAPCIE_RPSC_INT_FIFO_NOT_EMPTY_SHIFT</a>&#160;&#160;&#160;18</td></tr>
<tr class="memdesc:a5bb602a109560d8ef2a81760aaf6c0d0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Interrupt FIFO Empty Shift.  <a href="#a5bb602a109560d8ef2a81760aaf6c0d0">More...</a><br/></td></tr>
<tr class="separator:a5bb602a109560d8ef2a81760aaf6c0d0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a24935b2ccc22d16f695dbf4babbd5de2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a24935b2ccc22d16f695dbf4babbd5de2">XDMAPCIE_RPSC_INT_FIFO_OVERFLOW_SHIFT</a>&#160;&#160;&#160;19</td></tr>
<tr class="memdesc:a24935b2ccc22d16f695dbf4babbd5de2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Interrupt FIFO Overflow Shift.  <a href="#a24935b2ccc22d16f695dbf4babbd5de2">More...</a><br/></td></tr>
<tr class="separator:a24935b2ccc22d16f695dbf4babbd5de2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9b72b9b5361ff2a4f8ef4b58c5567b8a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a9b72b9b5361ff2a4f8ef4b58c5567b8a">XDMAPCIE_RPSC_COMP_TIMEOUT_SHIFT</a>&#160;&#160;&#160;20</td></tr>
<tr class="memdesc:a9b72b9b5361ff2a4f8ef4b58c5567b8a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Root Port Completion Timeout Shift.  <a href="#a9b72b9b5361ff2a4f8ef4b58c5567b8a">More...</a><br/></td></tr>
<tr class="separator:a9b72b9b5361ff2a4f8ef4b58c5567b8a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Root Port MSI Base Register bitmaps and masks</div></td></tr>
<tr class="memitem:aa7c2a15bd965cf4c40c6ef0467840f3c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#aa7c2a15bd965cf4c40c6ef0467840f3c">XDMAPCIE_RPMSIB_UPPER_MASK</a>&#160;&#160;&#160;0xFFFFFFFF</td></tr>
<tr class="memdesc:aa7c2a15bd965cf4c40c6ef0467840f3c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Upper 32 bits of 64 bit MSI Base Address.  <a href="#aa7c2a15bd965cf4c40c6ef0467840f3c">More...</a><br/></td></tr>
<tr class="separator:aa7c2a15bd965cf4c40c6ef0467840f3c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae442673affe69c584bfce0358edb8457"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae442673affe69c584bfce0358edb8457"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDMAPCIE_RPMSIB_UPPER_SHIFT</b>&#160;&#160;&#160;32	   /* Shift of Upper 32 bits */</td></tr>
<tr class="separator:ae442673affe69c584bfce0358edb8457"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac29f522978bcd22ada72cd32e6d2ad1f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#ac29f522978bcd22ada72cd32e6d2ad1f">XDMAPCIE_RPMSIB_LOWER_MASK</a>&#160;&#160;&#160;0xFFFFF000</td></tr>
<tr class="memdesc:ac29f522978bcd22ada72cd32e6d2ad1f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Lower 32 bits of 64 bit MSI Base Address.  <a href="#ac29f522978bcd22ada72cd32e6d2ad1f">More...</a><br/></td></tr>
<tr class="separator:ac29f522978bcd22ada72cd32e6d2ad1f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Root Port Error FIFO Read Register bitmaps and masks</div></td></tr>
<tr class="memitem:ae864fe8e0611b31480e861fb1a48582f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#ae864fe8e0611b31480e861fb1a48582f">XDMAPCIE_RPEFR_REQ_ID_MASK</a>&#160;&#160;&#160;0x0000FFFF</td></tr>
<tr class="memdesc:ae864fe8e0611b31480e861fb1a48582f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Requester of Error Msg.  <a href="#ae864fe8e0611b31480e861fb1a48582f">More...</a><br/></td></tr>
<tr class="separator:ae864fe8e0611b31480e861fb1a48582f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abd07ee76293490abe91819f9aef8bc56"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#abd07ee76293490abe91819f9aef8bc56">XDMAPCIE_RPEFR_ERR_TYPE_MASK</a>&#160;&#160;&#160;0x00030000</td></tr>
<tr class="memdesc:abd07ee76293490abe91819f9aef8bc56"><td class="mdescLeft">&#160;</td><td class="mdescRight">Type of Error.  <a href="#abd07ee76293490abe91819f9aef8bc56">More...</a><br/></td></tr>
<tr class="separator:abd07ee76293490abe91819f9aef8bc56"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a854a4541c2d8ccb05ddf14b86882ebe6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a854a4541c2d8ccb05ddf14b86882ebe6">XDMAPCIE_RPEFR_ERR_VALID_MASK</a>&#160;&#160;&#160;0x00040000</td></tr>
<tr class="memdesc:a854a4541c2d8ccb05ddf14b86882ebe6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Error Read Succeeded Status.  <a href="#a854a4541c2d8ccb05ddf14b86882ebe6">More...</a><br/></td></tr>
<tr class="separator:a854a4541c2d8ccb05ddf14b86882ebe6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aef51c54b8bc8f6695dee6c0260e6be08"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#aef51c54b8bc8f6695dee6c0260e6be08">XDMAPCIE_RPEFR_ERR_TYPE_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:aef51c54b8bc8f6695dee6c0260e6be08"><td class="mdescLeft">&#160;</td><td class="mdescRight">Type of Error Shift.  <a href="#aef51c54b8bc8f6695dee6c0260e6be08">More...</a><br/></td></tr>
<tr class="separator:aef51c54b8bc8f6695dee6c0260e6be08"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa0ea8677de2e2270781a5589086d7387"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#aa0ea8677de2e2270781a5589086d7387">XDMAPCIE_RPEFR_ERR_VALID_SHIFT</a>&#160;&#160;&#160;18</td></tr>
<tr class="memdesc:aa0ea8677de2e2270781a5589086d7387"><td class="mdescLeft">&#160;</td><td class="mdescRight">Error Read Succeeded Status Shift.  <a href="#aa0ea8677de2e2270781a5589086d7387">More...</a><br/></td></tr>
<tr class="separator:aa0ea8677de2e2270781a5589086d7387"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Root Port Interrupt FIFO Read 1 Register bitmaps and masks</div></td></tr>
<tr class="memitem:a4bece0606c363a0cc4778e270fdbb711"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a4bece0606c363a0cc4778e270fdbb711">XDMAPCIE_RPIFR1_REQ_ID_MASK</a>&#160;&#160;&#160;0x0000FFFF</td></tr>
<tr class="memdesc:a4bece0606c363a0cc4778e270fdbb711"><td class="mdescLeft">&#160;</td><td class="mdescRight">Requester Id of Interrupt Message.  <a href="#a4bece0606c363a0cc4778e270fdbb711">More...</a><br/></td></tr>
<tr class="separator:a4bece0606c363a0cc4778e270fdbb711"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7313a92a55b01bef8f6d0ee23015bd21"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a7313a92a55b01bef8f6d0ee23015bd21">XDMAPCIE_RPIFR1_MSI_ADDR_MASK</a>&#160;&#160;&#160;0x07FF0000</td></tr>
<tr class="memdesc:a7313a92a55b01bef8f6d0ee23015bd21"><td class="mdescLeft">&#160;</td><td class="mdescRight">MSI Address.  <a href="#a7313a92a55b01bef8f6d0ee23015bd21">More...</a><br/></td></tr>
<tr class="separator:a7313a92a55b01bef8f6d0ee23015bd21"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a00ef3ae153ecf6ef730c1d77f911b646"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a00ef3ae153ecf6ef730c1d77f911b646">XDMAPCIE_RPIFR1_INTR_LINE_MASK</a>&#160;&#160;&#160;0x18000000</td></tr>
<tr class="memdesc:a00ef3ae153ecf6ef730c1d77f911b646"><td class="mdescLeft">&#160;</td><td class="mdescRight">Intr Line Mask.  <a href="#a00ef3ae153ecf6ef730c1d77f911b646">More...</a><br/></td></tr>
<tr class="separator:a00ef3ae153ecf6ef730c1d77f911b646"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3c2291c58892e32fe6ef14e7affee793"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a3c2291c58892e32fe6ef14e7affee793">XDMAPCIE_RPIFR1_INTR_ASSERT_MASK</a>&#160;&#160;&#160;0x20000000</td></tr>
<tr class="memdesc:a3c2291c58892e32fe6ef14e7affee793"><td class="mdescLeft">&#160;</td><td class="mdescRight">Whether Interrupt INTx is asserted.  <a href="#a3c2291c58892e32fe6ef14e7affee793">More...</a><br/></td></tr>
<tr class="separator:a3c2291c58892e32fe6ef14e7affee793"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6a5ab88c6292ec6e362f74bd6c9cae4b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a6a5ab88c6292ec6e362f74bd6c9cae4b">XDMAPCIE_RPIFR1_MSIINTR_VALID_MASK</a>&#160;&#160;&#160;0x40000000</td></tr>
<tr class="memdesc:a6a5ab88c6292ec6e362f74bd6c9cae4b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Whether Interrupt is MSI or INTx.  <a href="#a6a5ab88c6292ec6e362f74bd6c9cae4b">More...</a><br/></td></tr>
<tr class="separator:a6a5ab88c6292ec6e362f74bd6c9cae4b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2e7d4992c3815b1b8e976cc90baa99e7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a2e7d4992c3815b1b8e976cc90baa99e7">XDMAPCIE_RPIFR1_INTR_VALID_MASK</a>&#160;&#160;&#160;0x80000000</td></tr>
<tr class="memdesc:a2e7d4992c3815b1b8e976cc90baa99e7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Read Succeeded Status.  <a href="#a2e7d4992c3815b1b8e976cc90baa99e7">More...</a><br/></td></tr>
<tr class="separator:a2e7d4992c3815b1b8e976cc90baa99e7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa13faabf819e0c4fdb157650e1db8ca1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#aa13faabf819e0c4fdb157650e1db8ca1">XDMAPCIE_RPIFR1_MSI_ADDR_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:aa13faabf819e0c4fdb157650e1db8ca1"><td class="mdescLeft">&#160;</td><td class="mdescRight">MSI Address Shift.  <a href="#aa13faabf819e0c4fdb157650e1db8ca1">More...</a><br/></td></tr>
<tr class="separator:aa13faabf819e0c4fdb157650e1db8ca1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa39c481cf7526edda33a09cdba1f525e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#aa39c481cf7526edda33a09cdba1f525e">XDMAPCIE_RPIFR1_MSIINTR_VALID_SHIFT</a>&#160;&#160;&#160;30</td></tr>
<tr class="memdesc:aa39c481cf7526edda33a09cdba1f525e"><td class="mdescLeft">&#160;</td><td class="mdescRight">MSI/INTx Interrupt Shift.  <a href="#aa39c481cf7526edda33a09cdba1f525e">More...</a><br/></td></tr>
<tr class="separator:aa39c481cf7526edda33a09cdba1f525e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abc20d6f07d915eeeda963f3bc44ce978"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#abc20d6f07d915eeeda963f3bc44ce978">XDMAPCIE_RPIFR1_INTR_VALID_SHIFT</a>&#160;&#160;&#160;31</td></tr>
<tr class="memdesc:abc20d6f07d915eeeda963f3bc44ce978"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Read Valid Shift.  <a href="#abc20d6f07d915eeeda963f3bc44ce978">More...</a><br/></td></tr>
<tr class="separator:abc20d6f07d915eeeda963f3bc44ce978"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Root Port Interrupt FIFO Read 2 Register bitmaps and masks</div></td></tr>
<tr class="memitem:a2806e420f58fa46b4c36e5c82d401e88"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a2806e420f58fa46b4c36e5c82d401e88">XDMAPCIE_RPIFR2_MSG_DATA_MASK</a>&#160;&#160;&#160;0x0000FFFF</td></tr>
<tr class="memdesc:a2806e420f58fa46b4c36e5c82d401e88"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pay Load for MSI Message.  <a href="#a2806e420f58fa46b4c36e5c82d401e88">More...</a><br/></td></tr>
<tr class="separator:a2806e420f58fa46b4c36e5c82d401e88"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">ECAM Address Register bitmaps and masks</div></td></tr>
<tr class="memitem:a01392488b9dbf0627dbeb7a09b1432c3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a01392488b9dbf0627dbeb7a09b1432c3">XDMAPCIE_ECAM_MASK</a>&#160;&#160;&#160;0x0FFFFFFF</td></tr>
<tr class="memdesc:a01392488b9dbf0627dbeb7a09b1432c3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mask of all valid bits.  <a href="#a01392488b9dbf0627dbeb7a09b1432c3">More...</a><br/></td></tr>
<tr class="separator:a01392488b9dbf0627dbeb7a09b1432c3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a60661e23fd3bed5e8b770add9f063829"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a60661e23fd3bed5e8b770add9f063829">XDMAPCIE_ECAM_BUS_MASK</a>&#160;&#160;&#160;0x0FF00000</td></tr>
<tr class="memdesc:a60661e23fd3bed5e8b770add9f063829"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bus Number Mask.  <a href="#a60661e23fd3bed5e8b770add9f063829">More...</a><br/></td></tr>
<tr class="separator:a60661e23fd3bed5e8b770add9f063829"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1997d2571a0cb4941e479fb6224bdc64"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a1997d2571a0cb4941e479fb6224bdc64">XDMAPCIE_ECAM_DEV_MASK</a>&#160;&#160;&#160;0x000F8000</td></tr>
<tr class="memdesc:a1997d2571a0cb4941e479fb6224bdc64"><td class="mdescLeft">&#160;</td><td class="mdescRight">Device Number Mask.  <a href="#a1997d2571a0cb4941e479fb6224bdc64">More...</a><br/></td></tr>
<tr class="separator:a1997d2571a0cb4941e479fb6224bdc64"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a51b79b2dfbcc14488c445e9aae992304"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a51b79b2dfbcc14488c445e9aae992304">XDMAPCIE_ECAM_FUN_MASK</a>&#160;&#160;&#160;0x00007000</td></tr>
<tr class="memdesc:a51b79b2dfbcc14488c445e9aae992304"><td class="mdescLeft">&#160;</td><td class="mdescRight">Function Number Mask.  <a href="#a51b79b2dfbcc14488c445e9aae992304">More...</a><br/></td></tr>
<tr class="separator:a51b79b2dfbcc14488c445e9aae992304"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9dcdef1ed03f2b5c78f704d169954761"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a9dcdef1ed03f2b5c78f704d169954761">XDMAPCIE_ECAM_REG_MASK</a>&#160;&#160;&#160;0x00000FFC</td></tr>
<tr class="memdesc:a9dcdef1ed03f2b5c78f704d169954761"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register Number Mask.  <a href="#a9dcdef1ed03f2b5c78f704d169954761">More...</a><br/></td></tr>
<tr class="separator:a9dcdef1ed03f2b5c78f704d169954761"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a25c8350c601c09e148dd36e91f826a0b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a25c8350c601c09e148dd36e91f826a0b">XDMAPCIE_ECAM_BYT_MASK</a>&#160;&#160;&#160;0x00000003</td></tr>
<tr class="memdesc:a25c8350c601c09e148dd36e91f826a0b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Byte Address Mask.  <a href="#a25c8350c601c09e148dd36e91f826a0b">More...</a><br/></td></tr>
<tr class="separator:a25c8350c601c09e148dd36e91f826a0b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a58302eb1c29983cc00d22602336a8ec9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a58302eb1c29983cc00d22602336a8ec9">XDMAPCIE_ECAM_BUS_SHIFT</a>&#160;&#160;&#160;20</td></tr>
<tr class="memdesc:a58302eb1c29983cc00d22602336a8ec9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bus Number Shift Value.  <a href="#a58302eb1c29983cc00d22602336a8ec9">More...</a><br/></td></tr>
<tr class="separator:a58302eb1c29983cc00d22602336a8ec9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a975246680a113dcf741dd9fb4fb213d4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a975246680a113dcf741dd9fb4fb213d4">XDMAPCIE_ECAM_DEV_SHIFT</a>&#160;&#160;&#160;15</td></tr>
<tr class="memdesc:a975246680a113dcf741dd9fb4fb213d4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Device Number Shift Value.  <a href="#a975246680a113dcf741dd9fb4fb213d4">More...</a><br/></td></tr>
<tr class="separator:a975246680a113dcf741dd9fb4fb213d4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a13d53dc924d12c53f0707697911176cb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a13d53dc924d12c53f0707697911176cb">XDMAPCIE_ECAM_FUN_SHIFT</a>&#160;&#160;&#160;12</td></tr>
<tr class="memdesc:a13d53dc924d12c53f0707697911176cb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Function Number Shift Value.  <a href="#a13d53dc924d12c53f0707697911176cb">More...</a><br/></td></tr>
<tr class="separator:a13d53dc924d12c53f0707697911176cb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afec4ab3c1c02e1155e7f94e3ddcae7c8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#afec4ab3c1c02e1155e7f94e3ddcae7c8">XDMAPCIE_ECAM_REG_SHIFT</a>&#160;&#160;&#160;2</td></tr>
<tr class="memdesc:afec4ab3c1c02e1155e7f94e3ddcae7c8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register Number Shift Value.  <a href="#afec4ab3c1c02e1155e7f94e3ddcae7c8">More...</a><br/></td></tr>
<tr class="separator:afec4ab3c1c02e1155e7f94e3ddcae7c8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a031b7ee7ec9670fc24971b71d63c66a2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xdmapcie__hw_8h.html#a031b7ee7ec9670fc24971b71d63c66a2">XDMAPCIE_ECAM_BYT_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:a031b7ee7ec9670fc24971b71d63c66a2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Byte Offset Shift Value.  <a href="#a031b7ee7ec9670fc24971b71d63c66a2">More...</a><br/></td></tr>
<tr class="separator:a031b7ee7ec9670fc24971b71d63c66a2"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="acdd10dcc061e19b4fc59bae614d5d623"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XDMAPCIE_ATU_LIMIT_ADDR&#160;&#160;&#160;0xFFFFFF</td>
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</div><div class="memdoc">

<p>IATU Limit Address Range. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#adac6261cddb63084c8ee87518e99edef">XDmaPcie_ReadRemoteConfigSpace()</a>.</p>

</div>
</div>
<a class="anchor" id="adb19a64b3049aecfb96ecbfaabb0ec4f"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XDMAPCIE_ATU_REGION_SIZE&#160;&#160;&#160;0x1000</td>
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      </table>
</div><div class="memdoc">

<p>IATU MAX Region Size. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#adac6261cddb63084c8ee87518e99edef">XDmaPcie_ReadRemoteConfigSpace()</a>.</p>

</div>
</div>
<a class="anchor" id="a51aeaa8592563052dfac4d5c7c5ee606"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XDMAPCIE_AXIBAR2PCIBAR_0L_OFFSET&#160;&#160;&#160;0x20C</td>
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      </table>
</div><div class="memdoc">

<p>AXIBAR to PCIBAR translation 0 lower 32 bits. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a2c9b0cae150260c8ee67c21c3e7cd372">XDmaPcie_GetLocalBusBar2PcieBar()</a>, and <a class="el" href="xdmapcie_8h.html#af399300a4c8de88e4545ec848acfbca3">XDmaPcie_SetLocalBusBar2PcieBar()</a>.</p>

</div>
</div>
<a class="anchor" id="a5c9801387aa82ecd82ef7eeb15224636"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XDMAPCIE_AXIBAR2PCIBAR_0U_OFFSET&#160;&#160;&#160;0x208</td>
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</div><div class="memdoc">

<p>AXIBAR 2 PCIBAR translation 0 upper 32 bits. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a2c9b0cae150260c8ee67c21c3e7cd372">XDmaPcie_GetLocalBusBar2PcieBar()</a>, and <a class="el" href="xdmapcie_8h.html#af399300a4c8de88e4545ec848acfbca3">XDmaPcie_SetLocalBusBar2PcieBar()</a>.</p>

</div>
</div>
<a class="anchor" id="aae54b8461f7378ac04fdeb5003a40f5e"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XDMAPCIE_AXIBAR2PCIBAR_1L_OFFSET&#160;&#160;&#160;0x214</td>
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      </table>
</div><div class="memdoc">

<p>AXIBAR to PCIBAR translation 1 lower 32 bits. </p>

</div>
</div>
<a class="anchor" id="a82dc968ee93525aa88ccf20114e44527"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XDMAPCIE_AXIBAR2PCIBAR_1U_OFFSET&#160;&#160;&#160;0x210</td>
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</div><div class="memdoc">

<p>AXIBAR to PCIBAR translation 1 upper 32 bits. </p>

</div>
</div>
<a class="anchor" id="ab53d13c64564b4668256c817f5e0068b"></a>
<div class="memitem">
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          <td class="memname">#define XDMAPCIE_AXIBAR2PCIBAR_2L_OFFSET&#160;&#160;&#160;0x21C</td>
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</div><div class="memdoc">

<p>AXIBAR to PCIBAR translation 2 lower 32 bits. </p>

</div>
</div>
<a class="anchor" id="a77ac31855b0e6d83ea7999a29a8ce4c8"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XDMAPCIE_AXIBAR2PCIBAR_2U_OFFSET&#160;&#160;&#160;0x218</td>
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</div><div class="memdoc">

<p>AXIBAR to PCIBAR translation 2 upper 32 bits. </p>

</div>
</div>
<a class="anchor" id="a6b5c1a0ce298b54d802396314a585981"></a>
<div class="memitem">
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          <td class="memname">#define XDMAPCIE_AXIBAR2PCIBAR_3L_OFFSET&#160;&#160;&#160;0x224</td>
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</div><div class="memdoc">

<p>AXIBAR to PCIBAR translation 3 lower 32 bits. </p>

</div>
</div>
<a class="anchor" id="ab73660262ed83e2db03302cc57a1b6aa"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XDMAPCIE_AXIBAR2PCIBAR_3U_OFFSET&#160;&#160;&#160;0x220</td>
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      </table>
</div><div class="memdoc">

<p>AXIBAR to PCIBAR translation 3 upper 32 bits. </p>

</div>
</div>
<a class="anchor" id="a59bbd07ab35b7dbe8534d41deba0490e"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XDMAPCIE_AXIBAR2PCIBAR_4L_OFFSET&#160;&#160;&#160;0x22C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AXIBAR to PCIBAR translation 4 lower 32 bits. </p>

</div>
</div>
<a class="anchor" id="a117eb6e0c55cf3eb474c087becaa3dfb"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XDMAPCIE_AXIBAR2PCIBAR_4U_OFFSET&#160;&#160;&#160;0x228</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AXIBAR to PCIBAR translation 4 upper 32 bits. </p>

</div>
</div>
<a class="anchor" id="ab63696750f01c882427fe3d0118756c5"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XDMAPCIE_AXIBAR2PCIBAR_5L_OFFSET&#160;&#160;&#160;0x234</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AXIBAR to PCIBAR translation 5 lower 32 bits. </p>

</div>
</div>
<a class="anchor" id="afae77b2b76afd561a3d35442a58215e4"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XDMAPCIE_AXIBAR2PCIBAR_5U_OFFSET&#160;&#160;&#160;0x230</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AXIBAR to PCIBAR translation 5 upper 32 bits. </p>

</div>
</div>
<a class="anchor" id="abcda754d0a61c43d447fadb67aaa7434"></a>
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          <td class="memname">#define XDMAPCIE_BI_ECAM_SIZE_MASK&#160;&#160;&#160;0x00070000</td>
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      </table>
</div><div class="memdoc">

<p>ECAM size. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a557a92506060fd460154426bd8c4870c">XDmaPcie_CfgInitialize()</a>, and <a class="el" href="xdmapcie_8h.html#a83357e666376be50d018b3e0d2d07acf">XDmaPcie_GetBridgeInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a4a8456b90f69f3ca2c3a8db12ea24ee8"></a>
<div class="memitem">
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          <td class="memname">#define XDMAPCIE_BI_ECAM_SIZE_SHIFT&#160;&#160;&#160;16</td>
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<p>PCIe ECAM Size Shift. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a557a92506060fd460154426bd8c4870c">XDmaPcie_CfgInitialize()</a>, and <a class="el" href="xdmapcie_8h.html#a83357e666376be50d018b3e0d2d07acf">XDmaPcie_GetBridgeInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a2799a39816b787225defc73fb71b174a"></a>
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          <td class="memname">#define XDMAPCIE_BI_GEN2_MASK&#160;&#160;&#160;0x00000001</td>
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      </table>
</div><div class="memdoc">

<p>PCIe Gen2 Speed Support Mask. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a83357e666376be50d018b3e0d2d07acf">XDmaPcie_GetBridgeInfo()</a>.</p>

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</div>
<a class="anchor" id="a3608f25f453e0135ff2e2bd6a160533c"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XDMAPCIE_BI_OFFSET&#160;&#160;&#160;0x130</td>
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<p>Bridge Info Register. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a557a92506060fd460154426bd8c4870c">XDmaPcie_CfgInitialize()</a>, and <a class="el" href="xdmapcie_8h.html#a83357e666376be50d018b3e0d2d07acf">XDmaPcie_GetBridgeInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a1341b82af3253d651248943c9c106b85"></a>
<div class="memitem">
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          <td class="memname">#define XDMAPCIE_BI_RP_MASK&#160;&#160;&#160;0x00000002</td>
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<p>PCIe Root Port Support. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a83357e666376be50d018b3e0d2d07acf">XDmaPcie_GetBridgeInfo()</a>.</p>

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</div>
<a class="anchor" id="ae4893d95f81629e3f530ac3f469865ec"></a>
<div class="memitem">
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          <td class="memname">#define XDMAPCIE_BI_RP_SHIFT&#160;&#160;&#160;1</td>
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<p>PCIe Root Port Shift. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a83357e666376be50d018b3e0d2d07acf">XDmaPcie_GetBridgeInfo()</a>.</p>

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</div>
<a class="anchor" id="ac59090cdcbe3d2156f27165a33e21d3c"></a>
<div class="memitem">
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          <td class="memname">#define XDMAPCIE_BL_BUS_MASK&#160;&#160;&#160;0x0000FF00</td>
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<p>Requester ID Bus Number. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a5f24eea699cbc956a9705034c5f12607">XDmaPcie_GetRequesterId()</a>.</p>

</div>
</div>
<a class="anchor" id="acc86d34d06e7fd42e5289dbc30aa680e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_BL_BUS_SHIFT&#160;&#160;&#160;8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Requester ID Bus Number Shift Value. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a5f24eea699cbc956a9705034c5f12607">XDmaPcie_GetRequesterId()</a>.</p>

</div>
</div>
<a class="anchor" id="a2b76774fe73eb5ddac64acd04d18a8f2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_BL_DEV_MASK&#160;&#160;&#160;0x000000F8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Requester ID Device Number. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a5f24eea699cbc956a9705034c5f12607">XDmaPcie_GetRequesterId()</a>.</p>

</div>
</div>
<a class="anchor" id="a77a9c17fea6e28f4daa1a40b933d38e0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_BL_DEV_SHIFT&#160;&#160;&#160;3</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Requester ID Device Number Shift Value. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a5f24eea699cbc956a9705034c5f12607">XDmaPcie_GetRequesterId()</a>.</p>

</div>
</div>
<a class="anchor" id="af5b647370bc05fa2a455f1569f7d5ef7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_BL_FUNC_MASK&#160;&#160;&#160;0x00000007</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Requester ID Function Number. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a5f24eea699cbc956a9705034c5f12607">XDmaPcie_GetRequesterId()</a>.</p>

</div>
</div>
<a class="anchor" id="a31d2fdd979d3087f69bd97eb52b4c499"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_BL_OFFSET&#160;&#160;&#160;0x140</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bus Location Register. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a5f24eea699cbc956a9705034c5f12607">XDmaPcie_GetRequesterId()</a>.</p>

</div>
</div>
<a class="anchor" id="acf6e6d7e43697c4b98bbf6f645f901dd"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_BL_PORT_MASK&#160;&#160;&#160;0x00FF0000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Requester ID Port Number. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a5f24eea699cbc956a9705034c5f12607">XDmaPcie_GetRequesterId()</a>.</p>

</div>
</div>
<a class="anchor" id="ac94b2bf9a1b1abfccc5c67b8e2fed743"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_BL_PORT_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Requester ID Bus Number Shift Value. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a5f24eea699cbc956a9705034c5f12607">XDmaPcie_GetRequesterId()</a>.</p>

</div>
</div>
<a class="anchor" id="a0728df5057cc9ea9a5042242192a59cf"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_BSC_ECAM_BUSY_MASK&#160;&#160;&#160;0x00000001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>ECAM Busy Status. </p>

</div>
</div>
<a class="anchor" id="ad1ca428956c846fb789bc4c9bb31bc58"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_BSC_GI_MASK&#160;&#160;&#160;0x00000100</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Global Interrupt Disable. </p>

<p>Referenced by <a class="el" href="xdmapcie__intr_8c.html#a3130feda681a6630a2c1d0cb77a2d868">XDmaPcie_DisableGlobalInterrupt()</a>, and <a class="el" href="xdmapcie__intr_8c.html#a60093f2ef3dd433de9da51dadc1e46bc">XDmaPcie_EnableGlobalInterrupt()</a>.</p>

</div>
</div>
<a class="anchor" id="a46af7762c004cff0605f71238f33039a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_BSC_GI_SHIFT&#160;&#160;&#160;8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Global Interrupt Disable Shift. </p>

<p>Referenced by <a class="el" href="xdmapcie__intr_8c.html#a3130feda681a6630a2c1d0cb77a2d868">XDmaPcie_DisableGlobalInterrupt()</a>, and <a class="el" href="xdmapcie__intr_8c.html#a60093f2ef3dd433de9da51dadc1e46bc">XDmaPcie_EnableGlobalInterrupt()</a>.</p>

</div>
</div>
<a class="anchor" id="ac669dec8e84593dc82387d7abb9e27ae"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_BSC_OFFSET&#160;&#160;&#160;0x134</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bridge Status and Control Register. </p>

<p>Referenced by <a class="el" href="xdmapcie__intr_8c.html#a3130feda681a6630a2c1d0cb77a2d868">XDmaPcie_DisableGlobalInterrupt()</a>, and <a class="el" href="xdmapcie__intr_8c.html#a60093f2ef3dd433de9da51dadc1e46bc">XDmaPcie_EnableGlobalInterrupt()</a>.</p>

</div>
</div>
<a class="anchor" id="a7b6e2b54068968f298376377cbc33176"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_BSC_RO_MASK&#160;&#160;&#160;0x00020000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>RW Permissions to RO Registers. </p>

</div>
</div>
<a class="anchor" id="a0b003ed96b00faaaece734e463b82f7c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_BSC_RO_SHIFT&#160;&#160;&#160;17</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>RO as RW Shift. </p>

</div>
</div>
<a class="anchor" id="a4823f914daacc6021a06d7784339f310"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_BSC_RW1C_MASK&#160;&#160;&#160;0x00010000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>RW Permissions to RW1C Registers. </p>

</div>
</div>
<a class="anchor" id="a2b1ce6f833d863b5d57787f4128ae155"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_BSC_RW1C_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>RW1C Shift. </p>

</div>
</div>
<a class="anchor" id="ac16ba889496220efc741c8253807c515"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_CFG_TLP_TYPE0&#160;&#160;&#160;0x4</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TYPE 0 to Config TLP. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#adac6261cddb63084c8ee87518e99edef">XDmaPcie_ReadRemoteConfigSpace()</a>.</p>

</div>
</div>
<a class="anchor" id="a401d3214b790655f8f2afd71c9ec99f7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_CFG_TLP_TYPE1&#160;&#160;&#160;0x5</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TYPE 1 to Config TLP. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#adac6261cddb63084c8ee87518e99edef">XDmaPcie_ReadRemoteConfigSpace()</a>.</p>

</div>
</div>
<a class="anchor" id="a60661e23fd3bed5e8b770add9f063829"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_ECAM_BUS_MASK&#160;&#160;&#160;0x0FF00000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bus Number Mask. </p>

</div>
</div>
<a class="anchor" id="a58302eb1c29983cc00d22602336a8ec9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_ECAM_BUS_SHIFT&#160;&#160;&#160;20</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bus Number Shift Value. </p>

</div>
</div>
<a class="anchor" id="a25c8350c601c09e148dd36e91f826a0b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_ECAM_BYT_MASK&#160;&#160;&#160;0x00000003</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Byte Address Mask. </p>

</div>
</div>
<a class="anchor" id="a031b7ee7ec9670fc24971b71d63c66a2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_ECAM_BYT_SHIFT&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Byte Offset Shift Value. </p>

</div>
</div>
<a class="anchor" id="a1997d2571a0cb4941e479fb6224bdc64"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_ECAM_DEV_MASK&#160;&#160;&#160;0x000F8000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Device Number Mask. </p>

</div>
</div>
<a class="anchor" id="a975246680a113dcf741dd9fb4fb213d4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_ECAM_DEV_SHIFT&#160;&#160;&#160;15</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Device Number Shift Value. </p>

</div>
</div>
<a class="anchor" id="a51b79b2dfbcc14488c445e9aae992304"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_ECAM_FUN_MASK&#160;&#160;&#160;0x00007000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Function Number Mask. </p>

</div>
</div>
<a class="anchor" id="a13d53dc924d12c53f0707697911176cb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_ECAM_FUN_SHIFT&#160;&#160;&#160;12</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Function Number Shift Value. </p>

</div>
</div>
<a class="anchor" id="a01392488b9dbf0627dbeb7a09b1432c3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_ECAM_MASK&#160;&#160;&#160;0x0FFFFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Mask of all valid bits. </p>

</div>
</div>
<a class="anchor" id="a9dcdef1ed03f2b5c78f704d169954761"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_ECAM_REG_MASK&#160;&#160;&#160;0x00000FFC</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register Number Mask. </p>

</div>
</div>
<a class="anchor" id="afec4ab3c1c02e1155e7f94e3ddcae7c8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_ECAM_REG_SHIFT&#160;&#160;&#160;2</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register Number Shift Value. </p>

</div>
</div>
<a class="anchor" id="a7844054c17cc8874eebaaedba9b24cf4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_IATU_LIMIT_ADDR_OFFSET&#160;&#160;&#160;0x010</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>ATU Lmit Address. </p>

</div>
</div>
<a class="anchor" id="ae73a480f3fc21d558ba967eb130456f4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_IATU_LWR_BASE_ADDR_OFFSET&#160;&#160;&#160;0x008</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>ATU Lower Base Address. </p>

</div>
</div>
<a class="anchor" id="afd733b204e82bc26f763f8b3b85297fa"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_IATU_MAX_ATU_SIZE_OFFSET&#160;&#160;&#160;0x020</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>ATU Max Size. </p>

</div>
</div>
<a class="anchor" id="a2b8df76648fe067cec116769e55a10f8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_IATU_PCIE_LWR_ADDR_OFFSET&#160;&#160;&#160;0x014</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PCIe Lower Address. </p>

</div>
</div>
<a class="anchor" id="a032ceff8d0b842bad143b0c64227d1f4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_IATU_PCIE_UPPER_ADDR_OFFSET&#160;&#160;&#160;0x018</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PCIe Upper Address. </p>

</div>
</div>
<a class="anchor" id="acbc85cd7d570931c9fc11b2b006f25ab"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_IATU_REGION_CNTRL_OFFSET&#160;&#160;&#160;0x004</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>EN/DE IATU transalation. </p>

</div>
</div>
<a class="anchor" id="a23f3dd742a5d5c16771362ae05fb5855"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_IATU_UPPER_BASE_ADDR_OFFSET&#160;&#160;&#160;0x00C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>ATU Upper Base Address. </p>

</div>
</div>
<a class="anchor" id="ac5bccd0f9b46204220d8d51aa94bd551"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_ID_CFG_COMPL_STATE_MASK&#160;&#160;&#160;0x000000E0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Cfg Completion Status Mask. </p>

</div>
</div>
<a class="anchor" id="aa3898ed9e90c9e23f9315693062a3991"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_ID_CFG_TIMEOUT_MASK&#160;&#160;&#160;0x00000100</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Cfg timeout Mask. </p>

</div>
</div>
<a class="anchor" id="a74b7f78c8f8f27be92d422ccfb084e07"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_ID_CLEAR_ALL_MASK&#160;&#160;&#160;0xFFFFFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Mask of all Interrupts. </p>

<p>Referenced by <a class="el" href="xdmapcie__rc__enumerate__example_8c.html#aa1e7ab3bea37defba5bf6590492c9b3c">PcieInitRootComplex()</a>.</p>

</div>
</div>
<a class="anchor" id="afe136278e0354b9ba85ba73226ce9e23"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_ID_CMPL_ABT_MASK&#160;&#160;&#160;0x01000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Slave completion Abort Mask. </p>

</div>
</div>
<a class="anchor" id="a3b34e886cec2892554cbf31cc08c9197"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_ID_CMPL_TIMEOUT_MASK&#160;&#160;&#160;0x00400000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Slave completion Time Mask. </p>

</div>
</div>
<a class="anchor" id="acb23423c511b625fdeeb7e43bb045c27"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_ID_CORRECTABLE_ERR_MASK&#160;&#160;&#160;0x00000200</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Correctable Error Mask. </p>

</div>
</div>
<a class="anchor" id="a12b13b8b5223de6bc6df7447ab6d3a68"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_ID_DECODE_ERR_MASK&#160;&#160;&#160;0x04000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Master Decode Error Interrupt Mask. </p>

</div>
</div>
<a class="anchor" id="a13b93ab0b7d234ac97041dc2db299290"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_ID_ECRC_ERR_MASK&#160;&#160;&#160;0x00000002</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Rx Packet CRC failed. </p>

</div>
</div>
<a class="anchor" id="a34952b92fd0bdec7cae59ffce16e83e8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_ID_FATAL_ERR_MASK&#160;&#160;&#160;0x00000800</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Fatal Error Mask. </p>

</div>
</div>
<a class="anchor" id="af1702905586d6770aa2222bf528953f7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_ID_HOT_RST_MASK&#160;&#160;&#160;0x00000008</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Hot Reset Mask. </p>

</div>
</div>
<a class="anchor" id="ae55e7ffef0ef619cd1ba62f0e7f6551d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_ID_ILL_BURST_MASK&#160;&#160;&#160;0x02000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Slave Illegal Burst Mask. </p>

</div>
</div>
<a class="anchor" id="adb47b94222ead79c34bfe67cb6666ba9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_ID_INTX_INTERRUPT&#160;&#160;&#160;0x00010000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>INTX Interrupt. </p>

</div>
</div>
<a class="anchor" id="a6393e69d63266d198bbd282fed4d1e97"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_ID_LINK_DOWN_MASK&#160;&#160;&#160;0x00000001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Link Down Mask. </p>

</div>
</div>
<a class="anchor" id="aea347b3278e7f818123e606172331b2a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_ID_MASTER_EP_MASK&#160;&#160;&#160;0x10000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Master Error Poison Mask. </p>

</div>
</div>
<a class="anchor" id="aeec993ac36af4e9a89c5a0d7f7c8cbed"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_ID_MSI_INTERRUPT&#160;&#160;&#160;0x00020000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MSI Interrupt. </p>

</div>
</div>
<a class="anchor" id="a9e758cb476b717c4d7e6a2d887eb6f3d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_ID_NONFATAL_ERR_MASK&#160;&#160;&#160;0x00000400</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Non-Fatal Error Mask. </p>

</div>
</div>
<a class="anchor" id="a1a466d7f94958ad960844918169a95ef"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_ID_OFFSET&#160;&#160;&#160;0x138</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Interrupt Decode Register. </p>

<p>Referenced by <a class="el" href="xdmapcie__intr_8c.html#a1ba2488b5b13dfebf7a3df93c300d67e">XDmaPcie_ClearPendingInterrupts()</a>, and <a class="el" href="xdmapcie__intr_8c.html#afbcdc92c0afe5f15363ceea6dd2472be">XDmaPcie_GetPendingInterrupts()</a>.</p>

</div>
</div>
<a class="anchor" id="ad8c3856f42ac333491d841cfabf27907"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_ID_SLAVE_ERR_MASK&#160;&#160;&#160;0x08000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Master Slave Error Interrupt Mask. </p>

</div>
</div>
<a class="anchor" id="a1a81495ce39f05d61fb1317b4bf4f739"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_ID_SLV_EP_MASK&#160;&#160;&#160;0x00800000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Slave Error Poison Mask. </p>

</div>
</div>
<a class="anchor" id="ae68bc7f69def3b43c55de8b3b2bac667"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_ID_STR_ERR_MASK&#160;&#160;&#160;0x00000004</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Streaming Error Mask. </p>

</div>
</div>
<a class="anchor" id="a7853190498c4f53cdfd68b584f99f082"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_ID_UNEXP_CMPL_MASK&#160;&#160;&#160;0x00200000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Slave Unexpected Completion Mask. </p>

</div>
</div>
<a class="anchor" id="abb39a730f4774f13c67530fde1d5047e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_ID_UNSUPP_CMPL_MASK&#160;&#160;&#160;0x00100000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Slave Unsupported Request Mask. </p>

</div>
</div>
<a class="anchor" id="a41b00f72c89e54b044acfcd7bb7dfc86"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_IM_DISABLE_ALL_MASK&#160;&#160;&#160;0x00000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Disable All Interrupts. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a557a92506060fd460154426bd8c4870c">XDmaPcie_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="ab18aeb506ecb660c694912cb6935c096"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_IM_ENABLE_ALL_MASK&#160;&#160;&#160;0xFFFFFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Enable All Interrupts. </p>

<p>Referenced by <a class="el" href="xdmapcie__rc__enumerate__example_8c.html#aa1e7ab3bea37defba5bf6590492c9b3c">PcieInitRootComplex()</a>.</p>

</div>
</div>
<a class="anchor" id="a241506bc1816800ebc206d77b9d26436"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_IM_OFFSET&#160;&#160;&#160;0x13C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Interrupt Mask Register. </p>

<p>Referenced by <a class="el" href="xdmapcie__intr_8c.html#a086244f1e8866721dbb016893814281a">XDmaPcie_DisableInterrupts()</a>, <a class="el" href="xdmapcie__intr_8c.html#a034dab86e9626ac44e222373d056f693">XDmaPcie_EnableInterrupts()</a>, and <a class="el" href="xdmapcie__intr_8c.html#a7f0db923538acc2ee66a3011f1abf32c">XDmaPcie_GetEnabledInterrupts()</a>.</p>

</div>
</div>
<a class="anchor" id="a1083266540141374178a8efd47a8c838"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_PCIE_CORE_OFFSET&#160;&#160;&#160;0x000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PCI Express hard core configuration register offset. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a0b168437da7bb05a2cdcbc2267df272d">XDmaPcie_ReadLocalConfigSpace()</a>, and <a class="el" href="xdmapcie_8h.html#aeedb6585a8dcbcc40443e7b90932ad6c">XDmaPcie_WriteLocalConfigSpace()</a>.</p>

</div>
</div>
<a class="anchor" id="a07918f0976ea05b659dcb48830024b94"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_PHYSC_DLA_MASK&#160;&#160;&#160;0x00080000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Directed Link Change change to reliability or Autonomus Mask. </p>

</div>
</div>
<a class="anchor" id="ae47139cb2b379d4bff359036aa42abe1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_PHYSC_DLA_SHIFT&#160;&#160;&#160;19</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Directed Link change to reliability or Autonomus Shift. </p>

</div>
</div>
<a class="anchor" id="ad0e15c8e4792b8fe09d23371bc640d7d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_PHYSC_DLC_MASK&#160;&#160;&#160;0x00300000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Directed Link change Mask. </p>

</div>
</div>
<a class="anchor" id="aaedcc562b141445a3e3d1ff902b0f181"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_PHYSC_DLC_SHIFT&#160;&#160;&#160;20</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Directed Link change Shift. </p>

</div>
</div>
<a class="anchor" id="a98d409214ea974e741462c5d0554ff04"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_PHYSC_DLW_MASK&#160;&#160;&#160;0x00030000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Directed Link Width to change Mask. </p>

</div>
</div>
<a class="anchor" id="ab5c738000b50589ca980af8b05060f2a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_PHYSC_DLW_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Directed Link Width to change Shift. </p>

</div>
</div>
<a class="anchor" id="a725a5843208630c43a47984e91e6abcc"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_PHYSC_DLWS_MASK&#160;&#160;&#160;0x00040000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Directed Link Width Speed to change Mask. </p>

</div>
</div>
<a class="anchor" id="a92f25d869be109d6d65ead06dfb95ced"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_PHYSC_DLWS_SHIFT&#160;&#160;&#160;18</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Directed Link Width Speed to change Shift. </p>

</div>
</div>
<a class="anchor" id="a515854000c3f9bc56e9f587d68cb4af8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_PHYSC_LANE_REV_MASK&#160;&#160;&#160;0x00000600</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Lane Reversal Mask. </p>

</div>
</div>
<a class="anchor" id="ad6de7d11a8a2ad86e322589d12eacae9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_PHYSC_LANE_REV_SHIFT&#160;&#160;&#160;9</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Lane Reversal Shift. </p>

</div>
</div>
<a class="anchor" id="aead4ac7cb9705e7cf69aa71f9b3fbaf4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_PHYSC_LINK_RATE_MASK&#160;&#160;&#160;0x00000001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Link Rate. </p>

</div>
</div>
<a class="anchor" id="afc16fa2f0ab33302ebf077134d3b7047"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_PHYSC_LINK_UP_MASK&#160;&#160;&#160;0x00000800</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Link Up Status Mask. </p>

</div>
</div>
<a class="anchor" id="a55c53bb702906f82360a637c3432e0f8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_PHYSC_LINK_UP_SHIFT&#160;&#160;&#160;11</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Link Up Status Shift. </p>

</div>
</div>
<a class="anchor" id="a190170032f01cf924d9c5fb21364ae2c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_PHYSC_LINK_WIDTH_MASK&#160;&#160;&#160;0x00000006</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Link Width Mask. </p>

</div>
</div>
<a class="anchor" id="ad95083dc0eab75d131ae07bea00232b3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_PHYSC_LINK_WIDTH_SHIFT&#160;&#160;&#160;1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Link Status Shift. </p>

</div>
</div>
<a class="anchor" id="a11060b116fe77cdcde667e7e40297356"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_PHYSC_LTSSM_STATE_MASK&#160;&#160;&#160;0x000001F8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LTSSM State Mask. </p>

</div>
</div>
<a class="anchor" id="a68853d48944ae42e9a42d2812fb58ae8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_PHYSC_LTSSM_STATE_SHIFT&#160;&#160;&#160;3</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LTSSM State Shift. </p>

</div>
</div>
<a class="anchor" id="a571a1cd55e8f810fb91fcfebc441ee46"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_PHYSC_OFFSET&#160;&#160;&#160;0x144</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Physical status and Control Register. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a3533208a920e43d2e9442ca9b02a22a3">XDmaPcie_GetPhyStatusCtrl()</a>.</p>

</div>
</div>
<a class="anchor" id="a736c70d6aa883f4d252670658e3b95ad"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDmaPcie_ReadReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;Xil_In32((BaseAddress) + (RegOffset))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Macro to read register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the PCIe. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Value of the register.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="xdmapcie__hw_8h.html#a736c70d6aa883f4d252670658e3b95ad" title="Macro to read register. ">XDmaPcie_ReadReg(u32 BaseAddress, u32 RegOffset)</a> </dd></dl>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a557a92506060fd460154426bd8c4870c">XDmaPcie_CfgInitialize()</a>, <a class="el" href="xdmapcie__intr_8c.html#a1ba2488b5b13dfebf7a3df93c300d67e">XDmaPcie_ClearPendingInterrupts()</a>, <a class="el" href="xdmapcie__intr_8c.html#a3130feda681a6630a2c1d0cb77a2d868">XDmaPcie_DisableGlobalInterrupt()</a>, <a class="el" href="xdmapcie__intr_8c.html#a086244f1e8866721dbb016893814281a">XDmaPcie_DisableInterrupts()</a>, <a class="el" href="xdmapcie__intr_8c.html#a60093f2ef3dd433de9da51dadc1e46bc">XDmaPcie_EnableGlobalInterrupt()</a>, <a class="el" href="xdmapcie__intr_8c.html#a034dab86e9626ac44e222373d056f693">XDmaPcie_EnableInterrupts()</a>, <a class="el" href="xdmapcie_8h.html#a83357e666376be50d018b3e0d2d07acf">XDmaPcie_GetBridgeInfo()</a>, <a class="el" href="xdmapcie__intr_8c.html#a7f0db923538acc2ee66a3011f1abf32c">XDmaPcie_GetEnabledInterrupts()</a>, <a class="el" href="xdmapcie_8h.html#a2c9b0cae150260c8ee67c21c3e7cd372">XDmaPcie_GetLocalBusBar2PcieBar()</a>, <a class="el" href="xdmapcie__intr_8c.html#afbcdc92c0afe5f15363ceea6dd2472be">XDmaPcie_GetPendingInterrupts()</a>, <a class="el" href="xdmapcie_8h.html#a3533208a920e43d2e9442ca9b02a22a3">XDmaPcie_GetPhyStatusCtrl()</a>, <a class="el" href="xdmapcie_8h.html#a5f24eea699cbc956a9705034c5f12607">XDmaPcie_GetRequesterId()</a>, <a class="el" href="xdmapcie_8h.html#afc77bc991235ea37d13d7bd07032584e">XDmaPcie_GetRootPortErrFIFOMsg()</a>, <a class="el" href="xdmapcie_8h.html#a54d41c333a761b1c8decb59c19f1ffc6">XDmaPcie_GetRootPortIntFIFOReg()</a>, <a class="el" href="xdmapcie_8h.html#a2baa98cfc13d1f4d209267e80808e3b8">XDmaPcie_GetRootPortStatusCtrl()</a>, <a class="el" href="xdmapcie_8h.html#ac61d1050938321b594087912a2272efb">XDmaPcie_GetVsecCapability()</a>, <a class="el" href="xdmapcie_8h.html#acf9acbd19090d9147cdad13913354fa6">XDmaPcie_GetVsecHeader()</a>, <a class="el" href="xdmapcie_8h.html#a0b168437da7bb05a2cdcbc2267df272d">XDmaPcie_ReadLocalConfigSpace()</a>, <a class="el" href="xdmapcie_8h.html#adac6261cddb63084c8ee87518e99edef">XDmaPcie_ReadRemoteConfigSpace()</a>, and <a class="el" href="xdmapcie_8h.html#ad47beee6caa44ae3f91979be9cd531bf">XDmaPcie_WriteRemoteConfigSpace()</a>.</p>

</div>
</div>
<a class="anchor" id="ae8f262322bca4ce8dd8ab88ebda2dedb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_REGION_EN&#160;&#160;&#160;0x90000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>EN for IATU Address Transalation. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#adac6261cddb63084c8ee87518e99edef">XDmaPcie_ReadRemoteConfigSpace()</a>.</p>

</div>
</div>
<a class="anchor" id="abd07ee76293490abe91819f9aef8bc56"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_RPEFR_ERR_TYPE_MASK&#160;&#160;&#160;0x00030000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Type of Error. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#afc77bc991235ea37d13d7bd07032584e">XDmaPcie_GetRootPortErrFIFOMsg()</a>.</p>

</div>
</div>
<a class="anchor" id="aef51c54b8bc8f6695dee6c0260e6be08"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_RPEFR_ERR_TYPE_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Type of Error Shift. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#afc77bc991235ea37d13d7bd07032584e">XDmaPcie_GetRootPortErrFIFOMsg()</a>.</p>

</div>
</div>
<a class="anchor" id="a854a4541c2d8ccb05ddf14b86882ebe6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_RPEFR_ERR_VALID_MASK&#160;&#160;&#160;0x00040000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Error Read Succeeded Status. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#afc77bc991235ea37d13d7bd07032584e">XDmaPcie_GetRootPortErrFIFOMsg()</a>.</p>

</div>
</div>
<a class="anchor" id="aa0ea8677de2e2270781a5589086d7387"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_RPEFR_ERR_VALID_SHIFT&#160;&#160;&#160;18</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Error Read Succeeded Status Shift. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#afc77bc991235ea37d13d7bd07032584e">XDmaPcie_GetRootPortErrFIFOMsg()</a>.</p>

</div>
</div>
<a class="anchor" id="a46d0aae62d5b3314d9eb4ef5830b4ec0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_RPEFR_OFFSET&#160;&#160;&#160;0x154</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Root Port Error FIFO Read Register. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a8ae44f206a94bf40daea49281112b46d">XDmaPcie_ClearRootPortErrFIFOMsg()</a>, and <a class="el" href="xdmapcie_8h.html#afc77bc991235ea37d13d7bd07032584e">XDmaPcie_GetRootPortErrFIFOMsg()</a>.</p>

</div>
</div>
<a class="anchor" id="ae864fe8e0611b31480e861fb1a48582f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_RPEFR_REQ_ID_MASK&#160;&#160;&#160;0x0000FFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Requester of Error Msg. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#afc77bc991235ea37d13d7bd07032584e">XDmaPcie_GetRootPortErrFIFOMsg()</a>.</p>

</div>
</div>
<a class="anchor" id="a3c2291c58892e32fe6ef14e7affee793"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_RPIFR1_INTR_ASSERT_MASK&#160;&#160;&#160;0x20000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Whether Interrupt INTx is asserted. </p>

</div>
</div>
<a class="anchor" id="a00ef3ae153ecf6ef730c1d77f911b646"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_RPIFR1_INTR_LINE_MASK&#160;&#160;&#160;0x18000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Intr Line Mask. </p>

</div>
</div>
<a class="anchor" id="a2e7d4992c3815b1b8e976cc90baa99e7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_RPIFR1_INTR_VALID_MASK&#160;&#160;&#160;0x80000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Interrupt Read Succeeded Status. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a54d41c333a761b1c8decb59c19f1ffc6">XDmaPcie_GetRootPortIntFIFOReg()</a>.</p>

</div>
</div>
<a class="anchor" id="abc20d6f07d915eeeda963f3bc44ce978"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_RPIFR1_INTR_VALID_SHIFT&#160;&#160;&#160;31</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Interrupt Read Valid Shift. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a54d41c333a761b1c8decb59c19f1ffc6">XDmaPcie_GetRootPortIntFIFOReg()</a>.</p>

</div>
</div>
<a class="anchor" id="a7313a92a55b01bef8f6d0ee23015bd21"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_RPIFR1_MSI_ADDR_MASK&#160;&#160;&#160;0x07FF0000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MSI Address. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a54d41c333a761b1c8decb59c19f1ffc6">XDmaPcie_GetRootPortIntFIFOReg()</a>.</p>

</div>
</div>
<a class="anchor" id="aa13faabf819e0c4fdb157650e1db8ca1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_RPIFR1_MSI_ADDR_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MSI Address Shift. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a54d41c333a761b1c8decb59c19f1ffc6">XDmaPcie_GetRootPortIntFIFOReg()</a>.</p>

</div>
</div>
<a class="anchor" id="a6a5ab88c6292ec6e362f74bd6c9cae4b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_RPIFR1_MSIINTR_VALID_MASK&#160;&#160;&#160;0x40000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Whether Interrupt is MSI or INTx. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a54d41c333a761b1c8decb59c19f1ffc6">XDmaPcie_GetRootPortIntFIFOReg()</a>.</p>

</div>
</div>
<a class="anchor" id="aa39c481cf7526edda33a09cdba1f525e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_RPIFR1_MSIINTR_VALID_SHIFT&#160;&#160;&#160;30</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MSI/INTx Interrupt Shift. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a54d41c333a761b1c8decb59c19f1ffc6">XDmaPcie_GetRootPortIntFIFOReg()</a>.</p>

</div>
</div>
<a class="anchor" id="a2d3fa8b6821762a92a973e4b1d341f12"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_RPIFR1_OFFSET&#160;&#160;&#160;0x158</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Root Port Interrupt FIFO Read1 Register. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a1a9e71d1904e3b6bfca811f5baec640c">XDmaPcie_ClearRootPortIntFIFOReg()</a>, and <a class="el" href="xdmapcie_8h.html#a54d41c333a761b1c8decb59c19f1ffc6">XDmaPcie_GetRootPortIntFIFOReg()</a>.</p>

</div>
</div>
<a class="anchor" id="a4bece0606c363a0cc4778e270fdbb711"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_RPIFR1_REQ_ID_MASK&#160;&#160;&#160;0x0000FFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Requester Id of Interrupt Message. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a54d41c333a761b1c8decb59c19f1ffc6">XDmaPcie_GetRootPortIntFIFOReg()</a>.</p>

</div>
</div>
<a class="anchor" id="a2806e420f58fa46b4c36e5c82d401e88"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_RPIFR2_MSG_DATA_MASK&#160;&#160;&#160;0x0000FFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Pay Load for MSI Message. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a54d41c333a761b1c8decb59c19f1ffc6">XDmaPcie_GetRootPortIntFIFOReg()</a>.</p>

</div>
</div>
<a class="anchor" id="ad5f6e8d589fe6f5a01e312a8f092799c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_RPIFR2_OFFSET&#160;&#160;&#160;0x15C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Root Port Interrupt FIFO Read2 Register. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a54d41c333a761b1c8decb59c19f1ffc6">XDmaPcie_GetRootPortIntFIFOReg()</a>.</p>

</div>
</div>
<a class="anchor" id="ac29f522978bcd22ada72cd32e6d2ad1f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_RPMSIB_LOWER_MASK&#160;&#160;&#160;0xFFFFF000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Lower 32 bits of 64 bit MSI Base Address. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a1641602833f00b16132be700a66e2f93">XDmaPcie_SetRootPortMSIBase()</a>.</p>

</div>
</div>
<a class="anchor" id="a39e3da3783cd1ae36538dda9353bd662"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_RPMSIB_LOWER_OFFSET&#160;&#160;&#160;0x150</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Root Port MSI Base 2 Register Lower 32 bits from 64 bit address are written. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a1641602833f00b16132be700a66e2f93">XDmaPcie_SetRootPortMSIBase()</a>.</p>

</div>
</div>
<a class="anchor" id="aa7c2a15bd965cf4c40c6ef0467840f3c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_RPMSIB_UPPER_MASK&#160;&#160;&#160;0xFFFFFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Upper 32 bits of 64 bit MSI Base Address. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a1641602833f00b16132be700a66e2f93">XDmaPcie_SetRootPortMSIBase()</a>.</p>

</div>
</div>
<a class="anchor" id="a2c7a2d9d74f6b92651fe50bddbb5e594"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_RPMSIB_UPPER_OFFSET&#160;&#160;&#160;0x14C</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Root Port MSI Base 1 Register Upper 32 bits from 64 bit address are written. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a1641602833f00b16132be700a66e2f93">XDmaPcie_SetRootPortMSIBase()</a>.</p>

</div>
</div>
<a class="anchor" id="ab96dc6e8195341e32b42ca36f3aec23e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_RPSC_BRIDGE_ENABLE_MASK&#160;&#160;&#160;0x00000001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Bridge Enable Mask. </p>

</div>
</div>
<a class="anchor" id="af965b436e06bf4ca8aa3c8cf860ace6b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_RPSC_COMP_TIMEOUT_MASK&#160;&#160;&#160;0x0FF00000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Root Port Completion Timeout. </p>

</div>
</div>
<a class="anchor" id="a9b72b9b5361ff2a4f8ef4b58c5567b8a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_RPSC_COMP_TIMEOUT_SHIFT&#160;&#160;&#160;20</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Root Port Completion Timeout Shift. </p>

</div>
</div>
<a class="anchor" id="abffbe554f8cc85db7abbd1cbe2b4dfe8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_RPSC_ERR_FIFO_NOT_EMPTY_MASK&#160;&#160;&#160;0x00010000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Root Port Error FIFO Not Empty. </p>

</div>
</div>
<a class="anchor" id="abe32d765694043ff1995db28e229b2a9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_RPSC_ERR_FIFO_NOT_EMPTY_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Root Port Error FIFO Empty Shift. </p>

</div>
</div>
<a class="anchor" id="a678edd87e3e899c48a60c127eb7638ae"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_RPSC_ERR_FIFO_OVERFLOW_MASK&#160;&#160;&#160;0x00020000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Root Port Error FIFO Overflow. </p>

</div>
</div>
<a class="anchor" id="a9337c811fae2354f9c20c3cd241cf600"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_RPSC_ERR_FIFO_OVERFLOW_SHIFT&#160;&#160;&#160;17</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Root Port Error FIFO Overflow Shift. </p>

</div>
</div>
<a class="anchor" id="a7070839d967cea172a8f994a1b518e5b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_RPSC_INT_FIFO_NOT_EMPTY_MASK&#160;&#160;&#160;0x00040000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Root Port Interrupt FIFO Not Empty. </p>

</div>
</div>
<a class="anchor" id="a5bb602a109560d8ef2a81760aaf6c0d0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_RPSC_INT_FIFO_NOT_EMPTY_SHIFT&#160;&#160;&#160;18</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Root Port Interrupt FIFO Empty Shift. </p>

</div>
</div>
<a class="anchor" id="a749e43cd6d57f047c7a5484ada878114"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_RPSC_INT_FIFO_OVERFLOW_MASK&#160;&#160;&#160;0x00080000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Root Port Interrupt FIFO Overflow. </p>

</div>
</div>
<a class="anchor" id="a24935b2ccc22d16f695dbf4babbd5de2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_RPSC_INT_FIFO_OVERFLOW_SHIFT&#160;&#160;&#160;19</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Root Port Interrupt FIFO Overflow Shift. </p>

</div>
</div>
<a class="anchor" id="a8e480ce2a44fd9f14991d2421c4db0c7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_RPSC_MASK&#160;&#160;&#160;0x0FFF0001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Root Port Register mask. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a1f829c82bb17dcc56648246fafa2eaa5">XDmaPcie_SetRootPortStatusCtrl()</a>.</p>

</div>
</div>
<a class="anchor" id="ab68d32651b96f4c8a6cc6c7549509c82"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_RPSC_OFFSET&#160;&#160;&#160;0x148</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Root Port Status &amp; Control Register. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a2baa98cfc13d1f4d209267e80808e3b8">XDmaPcie_GetRootPortStatusCtrl()</a>, and <a class="el" href="xdmapcie_8h.html#a1f829c82bb17dcc56648246fafa2eaa5">XDmaPcie_SetRootPortStatusCtrl()</a>.</p>

</div>
</div>
<a class="anchor" id="a77a6fe6cbb4114298960a620f0e6f7a3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_UP_CONFIG_CAPABLE&#160;&#160;&#160;0x00000004</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Up Config Capable. </p>

</div>
</div>
<a class="anchor" id="a405f9e3195f36f58bd6685bba2231ffb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_VSECC_ID_MASK&#160;&#160;&#160;0x0000FFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Vsec capability Id. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#ac61d1050938321b594087912a2272efb">XDmaPcie_GetVsecCapability()</a>.</p>

</div>
</div>
<a class="anchor" id="a848f1c9bd9cdd5b2b9100f46b7353edb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_VSECC_NEXT_MASK&#160;&#160;&#160;0xFFF00000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Offset to next capability. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#ac61d1050938321b594087912a2272efb">XDmaPcie_GetVsecCapability()</a>.</p>

</div>
</div>
<a class="anchor" id="a9e335708c508110cad0e5c36cacb9eac"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_VSECC_NEXT_SHIFT&#160;&#160;&#160;20</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Next capability offset shift. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#ac61d1050938321b594087912a2272efb">XDmaPcie_GetVsecCapability()</a>.</p>

</div>
</div>
<a class="anchor" id="a16f5d7b6b585ac5ac0fcd5189889c104"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_VSECC_OFFSET&#160;&#160;&#160;0x128</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VSEC Capability Register. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#ac61d1050938321b594087912a2272efb">XDmaPcie_GetVsecCapability()</a>.</p>

</div>
</div>
<a class="anchor" id="a34df2e3887910bf3d736e98a983dcdbf"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_VSECC_VER_MASK&#160;&#160;&#160;0x000F0000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Version of capability Structure. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#ac61d1050938321b594087912a2272efb">XDmaPcie_GetVsecCapability()</a>.</p>

</div>
</div>
<a class="anchor" id="a019c307ea457a54fe5cffb84f4f807bd"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_VSECC_VER_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VSEC Version shift. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#ac61d1050938321b594087912a2272efb">XDmaPcie_GetVsecCapability()</a>.</p>

</div>
</div>
<a class="anchor" id="ad729068100112d67c4a08830e6a12b4d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_VSECH_ID_MASK&#160;&#160;&#160;0x0000FFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Vsec structure Id. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#acf9acbd19090d9147cdad13913354fa6">XDmaPcie_GetVsecHeader()</a>.</p>

</div>
</div>
<a class="anchor" id="a1471191e3dbfee9c528d5c42a1f6691f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XDMAPCIE_VSECH_LEN_MASK&#160;&#160;&#160;0xFFF00000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Length of Vsec capability structure. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#acf9acbd19090d9147cdad13913354fa6">XDmaPcie_GetVsecHeader()</a>.</p>

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          <td class="memname">#define XDMAPCIE_VSECH_LEN_SHIFT&#160;&#160;&#160;20</td>
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<p>Vsec length shift. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#acf9acbd19090d9147cdad13913354fa6">XDmaPcie_GetVsecHeader()</a>.</p>

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          <td class="memname">#define XDMAPCIE_VSECH_OFFSET&#160;&#160;&#160;0x12C</td>
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<p>VSEC Header Register. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#acf9acbd19090d9147cdad13913354fa6">XDmaPcie_GetVsecHeader()</a>.</p>

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          <td class="memname">#define XDMAPCIE_VSECH_REV_MASK&#160;&#160;&#160;0x000F0000</td>
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<p>Vsec header version. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#acf9acbd19090d9147cdad13913354fa6">XDmaPcie_GetVsecHeader()</a>.</p>

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          <td class="memname">#define XDMAPCIE_VSECH_REV_SHIFT&#160;&#160;&#160;16</td>
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<p>Vsec version shift. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#acf9acbd19090d9147cdad13913354fa6">XDmaPcie_GetVsecHeader()</a>.</p>

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          <td class="memname">#define XDmaPcie_WriteReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
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        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset, </td>
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        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
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        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;Xil_Out32((BaseAddress) + (RegOffset), (Data))</td>
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<p>Macro to write register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the PCIe. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset. </td></tr>
    <tr><td class="paramname">Data</td><td>is the data to write.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void XDmaPcie_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) </dd></dl>

<p>Referenced by <a class="el" href="xdmapcie__intr_8c.html#a1ba2488b5b13dfebf7a3df93c300d67e">XDmaPcie_ClearPendingInterrupts()</a>, <a class="el" href="xdmapcie_8h.html#a8ae44f206a94bf40daea49281112b46d">XDmaPcie_ClearRootPortErrFIFOMsg()</a>, <a class="el" href="xdmapcie_8h.html#a1a9e71d1904e3b6bfca811f5baec640c">XDmaPcie_ClearRootPortIntFIFOReg()</a>, <a class="el" href="xdmapcie__intr_8c.html#a3130feda681a6630a2c1d0cb77a2d868">XDmaPcie_DisableGlobalInterrupt()</a>, <a class="el" href="xdmapcie__intr_8c.html#a086244f1e8866721dbb016893814281a">XDmaPcie_DisableInterrupts()</a>, <a class="el" href="xdmapcie__intr_8c.html#a60093f2ef3dd433de9da51dadc1e46bc">XDmaPcie_EnableGlobalInterrupt()</a>, <a class="el" href="xdmapcie__intr_8c.html#a034dab86e9626ac44e222373d056f693">XDmaPcie_EnableInterrupts()</a>, <a class="el" href="xdmapcie_8h.html#af399300a4c8de88e4545ec848acfbca3">XDmaPcie_SetLocalBusBar2PcieBar()</a>, <a class="el" href="xdmapcie_8h.html#a1641602833f00b16132be700a66e2f93">XDmaPcie_SetRootPortMSIBase()</a>, <a class="el" href="xdmapcie_8h.html#a1f829c82bb17dcc56648246fafa2eaa5">XDmaPcie_SetRootPortStatusCtrl()</a>, <a class="el" href="xdmapcie_8h.html#aeedb6585a8dcbcc40443e7b90932ad6c">XDmaPcie_WriteLocalConfigSpace()</a>, and <a class="el" href="xdmapcie_8h.html#ad47beee6caa44ae3f91979be9cd531bf">XDmaPcie_WriteRemoteConfigSpace()</a>.</p>

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